INTEL DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED IN THIS PATCH
WILL MEET YOUR REQUIREMENTS, OR THAT THE OPERATION OF THIS PATCH
WILL BE UNINTERRUPTED OR ERROR-FREE.

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quartus-24.3.1-1.18-readme.txt
Readme file for Intel(R) Quartus(R) Prime 24.3.1 Patch 1.18
Copyright (C) Intel Corporation 2019 All right reserved.
Patch created on April 15, 2025, 3:42 a.m.
Patch Case#: 16027170917
Patches included: 
Patches conflicted: 
Patch prerequisites: 

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Description:

Patch# 1.18: 
 This patch enables the Agilex 5 Triple Speed Ethernet IP with LVDS I/O Pin parameters. Once the patch is applied, you will see a new tab in the TSE IP GUI (Pin Settings). This tab will allow you to configure the LVDS SERDES IP parameters as required for your intended pin lock, ensuring proper routing to the correct I/O Pins,  please refer to LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs, Section 5.1.6.2.1 – HSIO Pin Index Number and Respective Channel Pin Selection, which outlines how channel pin selections map to HSIO pin index numbers. 




Caution - You must either have previously installed the
          Intel(R) Quartus(R) Prime 24.3.1 software or must
          install the Intel(R) Quartus(R) Prime 24.3.1 software
          before installing this patch. Otherwise, the patch will
          not be installed correctly and the Intel(R) Quartus(R) Prime
          software will not run properly.

Note:
<Patches included> - means this patch includes those patches. If you
    already installed those patches, you can safely install this new
    patch on top.
<Patches conflicted> - means this patch conflicts with those patches.
    If you have any of those patches installed, don't install this patch.
    Contact Intel for further support.