# x, Qx

Tells the compiler which processor features it may target, including which instruction sets and optimizations it may generate.

## Syntax

Linux: | -x code

macOS: | -x code

Windows: | /Qx code

## Arguments

code | Specifies a feature set that the compiler can target, including which instruction sets and optimizations it may generate. Many of the following descriptions refer to Intel® Streaming SIMD Extensions (Intel® SSE) and Supplemental Streaming SIMD Extensions (Intel® SSSE). Possible values are:
ALDERLAKE AMBERLAKE BROADWELL CANNONLAKE CASCADELAKE COFFEELAKE COOPERLAKE GOLDMONT GOLDMONT-PLUS HASWELL ICELAKE-CLIENT (or ICELAKE) ICELAKE-SERVER IVYBRIDGE KABYLAKE KNL KNM ROCKETLAKE SANDYBRIDGE SAPPHIRERAPIDS SILVERMONT SKYLAKE SKYLAKE-AVX512 TIGERLAKE TREMONT WHISKEYLAKE | May generate instructions for processors that support the specified Intel® processor or microarchitecture code name. Optimizes for the specified Intel® processor or microarchitecture code name. Keywords KNL and SILVERMONT are only available on Windows and Linux systems. Keyword ICELAKE is deprecated and may be removed in a future release.
COMMON-AVX512 | May generate Intel® Advanced Vector Extensions 512 (Intel® AVX-512) Foundation instructions, Intel® AVX-512 Conflict Detection Instructions (CDI), as well as the instructions enabled with CORE-AVX2. Optimizes for Intel® processors that support Intel® AVX-512 instructions.
CORE-AVX512 | May generate Intel® Advanced Vector Extensions 512 (Intel® AVX-512) Foundation instructions, Intel® AVX-512 Conflict Detection Instructions (CDI), Intel® AVX-512 Doubleword and Quadword Instructions (DQI), Intel® AVX-512 Byte and Word Instructions (BWI) and Intel® AVX-512 Vector Length Extensions (VLE), as well as the instructions enabled with CORE-AVX2. Optimizes for Intel® processors that support Intel® AVX-512 instructions.
CORE-AVX2 | May generate Intel® Advanced Vector Extensions 2 (Intel® AVX2), Intel® AVX, SSE4.2, SSE4.1, SSE3, SSE2, SSE, and SSSE3 instructions for Intel® processors. Optimizes for Intel® processors that support Intel® AVX2 instructions.
CORE-AVX-I | May generate the RDRND instruction, Intel® Advanced Vector Extensions (Intel® AVX), Intel® SSE4.2, SSE4.1, SSE3, SSE2, SSE, and SSSE3 instructions for Intel® processors. Optimizes for Intel® processors that support the RDRND instruction.
AVX | May generate Intel® Advanced Vector Extensions (Intel® AVX), Intel® SSE4.2, SSE4.1, SSE3, SSE2, SSE, and SSSE3 instructions for Intel® processors. Optimizes for Intel processors that support Intel® AVX instructions.
SSE4.2 | May generate Intel® SSE4 Efficient Accelerated String and Text Processing instructions, Intel® SSE4 Vectorizing Compiler and Media Accelerator, and Intel® SSE3, SSE2, SSE, and SSSE3 instructions for Intel® processors. Optimizes for Intel processors that support Intel® SSE4.2 instructions.
SSE4.1 | May generate Intel® SSE4 Vectorizing Compiler and Media Accelerator instructions for Intel® processors. May generate Intel® SSE4.1, SSE3, SSE2, SSE, and SSSE3 instructions for Intel processors that support Intel® SSE4.1 instructions.
ATOM_SSE4.2 | May generate MOVBE instructions for Intel® processors, depending on the setting of option -minstruction (Linux and macOS) or /Qinstruction (Windows). May also generate Intel® SSE4.2, SSE3, SSE2, and SSE instructions for Intel processors. Optimizes for Intel Atom® processors that support Intel® SSE4.2 and MOVBE instructions. This keyword is only available on Windows and Linux systems.
ATOM_SSSE3 | May generate MOVBE instructions for Intel® processors, depending on the setting of option -minstruction (Linux and macOS) or /Qinstruction (Windows). May also generate SSSE3, Intel® SSE3, SSE2, and SSE instructions for Intel processors. Optimizes for Intel Atom® processors that support Intel® SSE3 and MOVBE instructions. This keyword is only available on Windows and Linux systems.
SSSE3 | May generate SSSE3 and Intel® SSE3, SSE2, and SSE instructions for Intel® processors. Optimizes for Intel processors that support SSSE3 instructions. For macOS systems, this value is only supported on Intel® 64 architecture. This replaces value T, which is deprecated.
SSE3 | May generate Intel® SSE3, SSE2, and SSE instructions for Intel® processors. Optimizes for Intel processors that support Intel® SSE3 instructions. This value is not available on macOS systems.
SSE2 | May generate Intel® SSE2 and SSE instructions for Intel® processors. Optimizes for Intel processors that support Intel® SSE2 instructions. This setting is only supported for ifort. This value is not available on macOS systems.
You can also specify a Host. For more information, see option [Q]xHost.

## Default

varies | On Windows systems, if neither /Qx nor /arch is specified, the default target architecture supports Intel® SSE2 instructions. On Linux systems, if neither -x nor -m is specified, the default target architecture supports Intel® SSE2 instructions. The default on macOS systems is [Q]xSSSE3.

## Description

This option tells the compiler which processor features it may target, including which instruction sets and optimizations it may generate. It also enables optimizations in addition to Intel feature-specific optimizations.

The specialized code generated by this option may only run on a subset of Intel® processors.

The resulting executables created from these option code values can only be run on Intel® processors that support the indicated instruction set.

The binaries produced by these code values will run on Intel® processors that support the specified features.

Do not use code values to create binaries that will execute on a processor that is not compatible with the targeted processor. The resulting program may fail with an illegal instruction exception or display other unexpected behavior.

Compiling the main program with any of the code values produces binaries that display a fatal runtime error if they are executed on unsupported processors, including all non-Intel processors.

Compiler options m and arch produce binaries that should run on processors not made by Intel that implement the same capabilities as the corresponding Intel® processors.

The -x and /Qx options enable additional optimizations not enabled with options -m or /arch (nor with options -ax and /Qax).

Linux

Options -x and -m are mutually exclusive. If both are specified, the compiler uses the last one specified and generates a warning.

Windows

Options /Qx and /arch are mutually exclusive. If both are specified, the compiler uses the last one specified and generates a warning.

### Note

All settings except SSE2 do a CPU check. However, if you specify option -O0 (Linux and macOS) or option /Od (Windows), no CPU check is performed.

### Note

This option only applies to host compilation. When offloading is enabled, it does not impact device-specific compilation. Offloading can only be enabled when using ifx.

Product and Performance Information
Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex. Notice revision #20201201

## IDE Equivalent

Visual Studio: Code Generation > Intel Processor-Specific Optimization

## Alternate Options

None

Parent topic: Code Generation Options

## See Also

xHost, QxHost compiler option
ax, Qax compiler option
arch compiler option
march compiler option
minstruction, Qinstruction compiler option
m compiler option