# Intrinsics for Logical Operations

The prototypes for Intel® Advanced Vector Extensions 512 (Intel® AVX-512) intrinsics are located in the zmmintrin.h header file.
To use these intrinsics, include the immintrin.h file as follows:

    #include <immintrin.h>

variable | definition
--- | ---
src | source element to use based on writemask result
k | writemask used as a selector
a | first source vector element
b | second source vector element
c | third source vector element
imm | comparison predicate, which can be any of the following values: `_MM_CMPINT_EQ` - Equal `_MM_CMPINT_LT` - Less than `_MM_CMPINT_LE` - Less than or Equal `_MM_CMPINT_NE` - Not Equal `_MM_CMPINT_NLT` - Not Less than `_MM_CMPINT_GE` - Greater than or Equal `_MM_CMPINT_NLE` - Not Less than or Equal `_MM_CMPINT_GT` - Greater than

_mm_mask_andnot_pd

    __m128d _mm_mask_andnot_pd(__m128d src, __mmask8 k, __m128d a, __m128d b)

CPUID Flags: AVX512DQ, AVX512VL

Instruction(s): vandnpd

Compute the bitwise AND NOT of packed double-precision (64-bit) floating-point elements in a and b, and return the results using writemask k (elements are copied from src when the corresponding mask bit is not set).

_mm_maskz_andnot_pd

    __m128d _mm_maskz_andnot_pd(__mmask8 k, __m128d a, __m128d b)

CPUID Flags: AVX512DQ, AVX512VL

Instruction(s): vandnpd

Compute the bitwise AND NOT of packed double-precision (64-bit) floating-point elements in a and b, and return the results using zeromask k (elements are zeroed out when the corresponding mask bit is not set).

_mm256_mask_andnot_pd

    __m256d _mm256_mask_andnot_pd(__m256d src, __mmask8 k, __m256d a, __m256d b)

CPUID Flags: AVX512DQ, AVX512VL

Instruction(s): vandnpd

Compute the bitwise AND NOT of packed double-precision (64-bit) floating-point elements in a and b, and return the results using writemask k (elements are copied from src when the corresponding mask bit is not set).

_mm256_maskz_andnot_pd

    __m256d _mm256_maskz_andnot_pd(__mmask8 k, __m256d a, __m256d b)

CPUID Flags: AVX512DQ, AVX512VL

Instruction(s): vandnpd

Compute the bitwise AND NOT of packed double-precision (64-bit) floating-point elements in a and b, and return the results using zeromask k (elements are zeroed out when the corresponding mask bit is not set).

_mm512_andnot_pd

    __m512d _mm512_andnot_pd(__m512d a, __m512d b)

CPUID Flags: AVX512DQ

Instruction(s): vandnpd

Compute the bitwise AND NOT of packed double-precision (64-bit) floating-point elements in a and b, and return the results.

_mm512_mask_andnot_pd

    __m512d _mm512_mask_andnot_pd(__m512d src, __mmask8 k, __m512d a, __m512d b)

CPUID Flags: AVX512DQ

Instruction(s): vandnpd

Compute the bitwise AND NOT of packed double-precision (64-bit) floating-point elements in a and b, and return the results using writemask k (elements are copied from src when the corresponding mask bit is not set).

_mm512_maskz_andnot_pd

    __m512d _mm512_maskz_andnot_pd(__mmask8 k, __m512d a, __m512d b)

CPUID Flags: AVX512DQ

Instruction(s): vandnpd

Compute the bitwise AND NOT of packed double-precision (64-bit) floating-point elements in a and b, and return the results using zeromask k (elements are zeroed out when the corresponding mask bit is not set).

_mm_mask_andnot_ps

    __m128 _mm_mask_andnot_ps(__m128 src, __mmask8 k, __m128 a, __m128 b)

CPUID Flags: AVX512DQ, AVX512VL

Instruction(s): vandnps

Compute the bitwise AND NOT of packed single-precision (32-bit) floating-point elements in a and b, and return the results using writemask k (elements are copied from src when the corresponding mask bit is not set).

_mm_maskz_andnot_ps

    __m128 _mm_maskz_andnot_ps(__mmask8 k, __m128 a, __m128 b)

CPUID Flags: AVX512DQ, AVX512VL

Instruction(s): vandnps

Compute the bitwise AND NOT of packed single-precision (32-bit) floating-point elements in a and b, and return the results using zeromask k (elements are zeroed out when the corresponding mask bit is not set).

_mm256_mask_andnot_ps

    __m256 _mm256_mask_andnot_ps(__m256 src, __mmask8 k, __m256 a, __m256 b)

CPUID Flags: AVX512DQ, AVX512VL

Instruction(s): vandnps

Compute the bitwise AND NOT of packed single-precision (32-bit) floating-point elements in a and b, and return the results using writemask k (elements are copied from src when the corresponding mask bit is not set).

_mm256_maskz_andnot_ps

    __m256 _mm256_maskz_andnot_ps(__mmask8 k, __m256 a, __m256 b)

CPUID Flags: AVX512DQ, AVX512VL

Instruction(s): vandnps

Compute the bitwise AND NOT of packed single-precision (32-bit) floating-point elements in a and b, and return the results using zeromask k (elements are zeroed out when the corresponding mask bit is not set).

_mm512_andnot_ps

    __m512 _mm512_andnot_ps(__m512 a, __m512 b)

CPUID Flags: AVX512DQ

Instruction(s): vandnps

Compute the bitwise AND NOT of packed single-precision (32-bit) floating-point elements in a and b, and return the results.

_mm512_mask_andnot_ps

    __m512 _mm512_mask_andnot_ps(__m512 src, __mmask16 k, __m512 a, __m512 b)

CPUID Flags: AVX512DQ

Instruction(s): vandnps

Compute the bitwise AND NOT of packed single-precision (32-bit) floating-point elements in a and b, and return the results using writemask k (elements are copied from src when the corresponding mask bit is not set).

_mm512_maskz_andnot_ps

    __m512 _mm512_maskz_andnot_ps(__mmask16 k, __m512 a, __m512 b)

CPUID Flags: AVX512DQ

Instruction(s): vandnps

Compute the bitwise AND NOT of packed single-precision (32-bit) floating-point elements in a and b, and return the results using zeromask k (elements are zeroed out when the corresponding mask bit is not set).

_mm_mask_and_pd

    __m128d _mm_mask_and_pd(__m128d src, __mmask8 k, __m128d a, __m128d b)

CPUID Flags: AVX512DQ, AVX512VL

Instruction(s): vandpd

Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in a and b, and return the results using writemask k (elements are copied from src when the corresponding mask bit is not set).

_mm_maskz_and_pd

    __m128d _mm_maskz_and_pd(__mmask8 k, __m128d a, __m128d b)

CPUID Flags: AVX512DQ, AVX512VL

Instruction(s): vandpd

Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in a and b, and return the results using zeromask k (elements are zeroed out when the corresponding mask bit is not set).

_mm256_mask_and_pd

    __m256d _mm256_mask_and_pd(__m256d src, __mmask8 k, __m256d a, __m256d b)

CPUID Flags: AVX512DQ, AVX512VL

Instruction(s): vandpd

Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in a and b, and return the results using writemask k (elements are copied from src when the corresponding mask bit is not set).

_mm256_maskz_and_pd

    __m256d _mm256_maskz_and_pd(__mmask8 k, __m256d a, __m256d b)

CPUID Flags: AVX512DQ, AVX512VL

Instruction(s): vandpd

Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in a and b, and return the results using zeromask k (elements are zeroed out when the corresponding mask bit is not set).

_mm512_and_pd

    __m512d _mm512_and_pd(__m512d a, __m512d b)

CPUID Flags: AVX512DQ

Instruction(s): vandpd

Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in a and b, and return the results.

_mm512_mask_and_pd

    __m512d _mm512_mask_and_pd(__m512d src, __mmask8 k, __m512d a, __m512d b)

CPUID Flags: AVX512DQ

Instruction(s): vandpd

Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in a and b, and return the results using writemask k (elements are copied from src when the corresponding mask bit is not set).

_mm512_maskz_and_pd

    __m512d _mm512_maskz_and_pd(__mmask8 k, __m512d a, __m512d b)

CPUID Flags: AVX512DQ

Instruction(s): vandpd

Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in a and b, and return the results using zeromask k (elements are zeroed out when the corresponding mask bit is not set).

_mm_mask_and_ps

    __m128 _mm_mask_and_ps(__m128 src, __mmask8 k, __m128 a, __m128 b)

CPUID Flags: AVX512DQ, AVX512VL

Instruction(s): vandps

Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in a and b, and return the results using writemask k (elements are copied from src when the corresponding mask bit is not set).

_mm_maskz_and_ps

    __m128 _mm_maskz_and_ps(__mmask8 k, __m128 a, __m128 b)

CPUID Flags: AVX512DQ, AVX512VL

Instruction(s): vandps

Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in a and b, and return the results using zeromask k (elements are zeroed out when the corresponding mask bit is not set).

_mm256_mask_and_ps

    __m256 _mm256_mask_and_ps(__m256 src, __mmask8 k, __m256 a, __m256 b)

CPUID Flags: AVX512DQ, AVX512VL

Instruction(s): vandps

Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in a and b, and return the results using writemask k (elements are copied from src when the corresponding mask bit is not set).

_mm256_maskz_and_ps

    __m256 _mm256_maskz_and_ps(__mmask8 k, __m256 a, __m256 b)

CPUID Flags: AVX512DQ, AVX512VL

Instruction(s): vandps

Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in a and b, and return the results using zeromask k (elements are zeroed out when the corresponding mask bit is not set).

_mm512_and_ps

    __m512 _mm512_and_ps(__m512 a, __m512 b)

CPUID Flags: AVX512DQ

Instruction(s): vandps

Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in a and b, and return the results.

_mm512_mask_and_ps

    __m512 _mm512_mask_and_ps(__m512 src, __mmask16 k, __m512 a, __m512 b)

CPUID Flags: AVX512DQ

Instruction(s): vandps

Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in a and b, and return the results using writemask k (elements are copied from src when the corresponding mask bit is not set).

_mm512_maskz_and_ps

    __m512 _mm512_maskz_and_ps(__mmask16 k, __m512 a, __m512 b)

CPUID Flags: AVX512DQ

Instruction(s): vandps

Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in a and b, and return the results using zeromask k (elements are zeroed out when the corresponding mask bit is not set).

_mm_mask_or_pd

    __m128d _mm_mask_or_pd(__m128d src, __mmask8 k, __m128d a, __m128d b)

CPUID Flags: AVX512DQ, AVX512VL

Instruction(s): vorpd

Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in a and b, and return the results using writemask k (elements are copied from src when the corresponding mask bit is not set).

_mm_maskz_or_pd

    __m128d _mm_maskz_or_pd(__mmask8 k, __m128d a, __m128d b)

CPUID Flags: AVX512DQ, AVX512VL

Instruction(s): vorpd

Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in a and b, and return the results using zeromask k (elements are zeroed out when the corresponding mask bit is not set).

_mm256_mask_or_pd

    __m256d _mm256_mask_or_pd(__m256d src, __mmask8 k, __m256d a, __m256d b)

CPUID Flags: AVX512DQ, AVX512VL

Instruction(s): vorpd

Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in a and b, and return the results using writemask k (elements are copied from src when the corresponding mask bit is not set).

_mm256_maskz_or_pd

    __m256d _mm256_maskz_or_pd(__mmask8 k, __m256d a, __m256d b)

CPUID Flags: AVX512DQ, AVX512VL

Instruction(s): vorpd

Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in a and b, and return the results using zeromask k (elements are zeroed out when the corresponding mask bit is not set).

_mm512_mask_or_pd

    __m512d _mm512_mask_or_pd(__m512d src, __mmask8 k, __m512d a, __m512d b)

CPUID Flags: AVX512DQ

Instruction(s): vorpd

Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in a and b, and return the results using writemask k (elements are copied from src when the corresponding mask bit is not set).

_mm512_maskz_or_pd

    __m512d _mm512_maskz_or_pd(__mmask8 k, __m512d a, __m512d b)

CPUID Flags: AVX512DQ

Instruction(s): vorpd

Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in a and b, and return the results using zeromask k (elements are zeroed out when the corresponding mask bit is not set).

_mm512_or_pd

    __m512d _mm512_or_pd(__m512d a, __m512d b)

CPUID Flags: AVX512DQ

Instruction(s): vorpd

Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in a and b, and return the results.

_mm_mask_or_ps

    __m128 _mm_mask_or_ps(__m128 src, __mmask8 k, __m128 a, __m128 b)

CPUID Flags: AVX512DQ, AVX512VL

Instruction(s): vorps

Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in a and b, and return the results using writemask k (elements are copied from src when the corresponding mask bit is not set).

_mm_maskz_or_ps

    __m128 _mm_maskz_or_ps(__mmask8 k, __m128 a, __m128 b)

CPUID Flags: AVX512DQ, AVX512VL

Instruction(s): vorps

Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in a and b, and return the results using zeromask k (elements are zeroed out when the corresponding mask bit is not set).

_mm256_mask_or_ps

    __m256 _mm256_mask_or_ps(__m256 src, __mmask8 k, __m256 a, __m256 b)

CPUID Flags: AVX512DQ, AVX512VL

Instruction(s): vorps

Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in a and b, and return the results using writemask k (elements are copied from src when the corresponding mask bit is not set).

_mm256_maskz_or_ps

    __m256 _mm256_maskz_or_ps(__mmask8 k, __m256 a, __m256 b)

CPUID Flags: AVX512DQ, AVX512VL

Instruction(s): vorps

Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in a and b, and return the results using zeromask k (elements are zeroed out when the corresponding mask bit is not set).

_mm512_mask_or_ps

    __m512 _mm512_mask_or_ps(__m512 src, __mmask16 k, __m512 a, __m512 b)

CPUID Flags: AVX512DQ

Instruction(s): vorps

Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in a and b, and return the results using writemask k (elements are copied from src when the corresponding mask bit is not set).

_mm512_maskz_or_ps

    __m512 _mm512_maskz_or_ps(__mmask16 k, __m512 a, __m512 b)

CPUID Flags: AVX512DQ

Instruction(s): vorps

Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in a and b, and return the results using zeromask k (elements are zeroed out when the corresponding mask bit is not set).

_mm512_or_ps

    __m512 _mm512_or_ps(__m512 a, __m512 b)

CPUID Flags: AVX512DQ

Instruction(s): vorps

Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in a and b, and return the results.

_mm_mask_xor_pd

    __m128d _mm_mask_xor_pd(__m128d src, __mmask8 k, __m128d a, __m128d b)

CPUID Flags: AVX512DQ, AVX512VL

Instruction(s): vxorpd

Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in a and b, and return the results using writemask k (elements are copied from src when the corresponding mask bit is not set).

_mm_maskz_xor_pd

    __m128d _mm_maskz_xor_pd(__mmask8 k, __m128d a, __m128d b)

CPUID Flags: AVX512DQ, AVX512VL

Instruction(s): vxorpd

Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in a and b, and return the results using zeromask k (elements are zeroed out when the corresponding mask bit is not set).

_mm256_mask_xor_pd

    __m256d _mm256_mask_xor_pd(__m256d src, __mmask8 k, __m256d a, __m256d b)

CPUID Flags: AVX512DQ, AVX512VL

Instruction(s): vxorpd

Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in a and b, and return the results using writemask k (elements are copied from src when the corresponding mask bit is not set).

_mm256_maskz_xor_pd

    __m256d _mm256_maskz_xor_pd(__mmask8 k, __m256d a, __m256d b)

CPUID Flags: AVX512DQ, AVX512VL

Instruction(s): vxorpd

Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in a and b, and return the results using zeromask k (elements are zeroed out when the corresponding mask bit is not set).

_mm512_mask_xor_pd

    __m512d _mm512_mask_xor_pd(__m512d src, __mmask8 k, __m512d a, __m512d b)

CPUID Flags: AVX512DQ

Instruction(s): vxorpd

Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in a and b, and return the results using writemask k (elements are copied from src when the corresponding mask bit is not set).

_mm512_maskz_xor_pd

    __m512d _mm512_maskz_xor_pd(__mmask8 k, __m512d a, __m512d b)

CPUID Flags: AVX512DQ

Instruction(s): vxorpd

Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in a and b, and return the results using zeromask k (elements are zeroed out when the corresponding mask bit is not set).

_mm512_xor_pd

    __m512d _mm512_xor_pd(__m512d a, __m512d b)

CPUID Flags: AVX512DQ

Instruction(s): vxorpd

Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in a and b, and return the results.

_mm_mask_xor_ps

    __m128 _mm_mask_xor_ps(__m128 src, __mmask8 k, __m128 a, __m128 b)

CPUID Flags: AVX512DQ, AVX512VL

Instruction(s): vxorps

Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in a and b, and return the results using writemask k (elements are copied from src when the corresponding mask bit is not set).

_mm_maskz_xor_ps

    __m128 _mm_maskz_xor_ps(__mmask8 k, __m128 a, __m128 b)

CPUID Flags: AVX512DQ, AVX512VL

Instruction(s): vxorps

Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in a and b, and return the results using zeromask k (elements are zeroed out when the corresponding mask bit is not set).

_mm256_mask_xor_ps

    __m256 _mm256_mask_xor_ps(__m256 src, __mmask8 k, __m256 a, __m256 b)

CPUID Flags: AVX512DQ, AVX512VL

Instruction(s): vxorps

Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in a and b, and return the results using writemask k (elements are copied from src when the corresponding mask bit is not set).

_mm256_maskz_xor_ps

    __m256 _mm256_maskz_xor_ps(__mmask8 k, __m256 a, __m256 b)

CPUID Flags: AVX512DQ, AVX512VL

Instruction(s): vxorps

Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in a and b, and return the results using zeromask k (elements are zeroed out when the corresponding mask bit is not set).

_mm512_mask_xor_ps

    __m512 _mm512_mask_xor_ps(__m512 src, __mmask16 k, __m512 a, __m512 b)

CPUID Flags: AVX512DQ

Instruction(s): vxorps

Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in a and b, and return the results using writemask k (elements are copied from src when the corresponding mask bit is not set).

_mm512_maskz_xor_ps

    __m512 _mm512_maskz_xor_ps(__mmask16 k, __m512 a, __m512 b)

CPUID Flags: AVX512DQ

Instruction(s): vxorps

Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in a and b, and return the results using zeromask k (elements are zeroed out when the corresponding mask bit is not set).

_mm512_xor_ps

    __m512 _mm512_xor_ps(__m512 a, __m512 b)

CPUID Flags: AVX512DQ

Instruction(s): vxorps

Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in a and b, and return the results.

_mm_mask_and_epi32

    __m128i _mm_mask_and_epi32(__m128i src, __mmask8 k, __m128i a, __m128i b)

CPUID Flags: AVX512F, AVX512VL

Instruction(s): vpandd

Compute the bitwise AND of packed 32-bit integers in a and b, and return the results using writemask k (elements are copied from src when the corresponding mask bit is not set).

_mm_maskz_and_epi32

    __m128i _mm_maskz_and_epi32(__mmask8 k, __m128i a, __m128i b)

CPUID Flags: AVX512F, AVX512VL

Instruction(s): vpandd

Compute the bitwise AND of packed 32-bit integers in a and b, and return the results using zeromask k (elements are zeroed out when the corresponding mask bit is not set).

_mm256_mask_and_epi32

    __m256i _mm256_mask_and_epi32(__m256i src, __mmask8 k, __m256i a, __m256i b)

CPUID Flags: AVX512F, AVX512VL

Instruction(s): vpandd

Compute the bitwise AND of packed 32-bit integers in a and b, and return the results using writemask k (elements are copied from src when the corresponding mask bit is not set).

_mm256_maskz_and_epi32

    __m256i _mm256_maskz_and_epi32(__mmask8 k, __m256i a, __m256i b)

CPUID Flags: AVX512F, AVX512VL

Instruction(s): vpandd

Compute the bitwise AND of packed 32-bit integers in a and b, and return the results using zeromask k (elements are zeroed out when the corresponding mask bit is not set).

_mm_mask_andnot_epi32

    __m128i _mm_mask_andnot_epi32(__m128i src, __mmask8 k, __m128i a, __m128i b)

CPUID Flags: AVX512F, AVX512VL

Instruction(s): vpandnd

Compute the bitwise AND NOT of packed 32-bit integers in a and b, and return the results using writemask k (elements are copied from src when the corresponding mask bit is not set).

_mm_maskz_andnot_epi32

    __m128i _mm_maskz_andnot_epi32(__mmask8 k, __m128i a, __m128i b)

CPUID Flags: AVX512F, AVX512VL

Instruction(s): vpandnd

Compute the bitwise AND NOT of packed 32-bit integers in a and b, and return the results using zeromask k (elements are zeroed out when the corresponding mask bit is not set).

_mm256_mask_andnot_epi32

    __m256i _mm256_mask_andnot_epi32(__m256i src, __mmask8 k, __m256i a, __m256i b)

CPUID Flags: AVX512F, AVX512VL

Instruction(s): vpandnd

Compute the bitwise AND NOT of packed 32-bit integers in a and b, and return the results using writemask k (elements are copied from src when the corresponding mask bit is not set).

_mm256_maskz_andnot_epi32

    __m256i _mm256_maskz_andnot_epi32(__mmask8 k, __m256i a, __m256i b)

CPUID Flags: AVX512F, AVX512VL

Instruction(s): vpandnd

Compute the bitwise AND NOT of packed 32-bit integers in a and b, and return the results using zeromask k (elements are zeroed out when the corresponding mask bit is not set).

_mm_mask_andnot_epi64

    __m128i _mm_mask_andnot_epi64(__m128i src, __mmask8 k, __m128i a, __m128i b)

CPUID Flags: AVX512F, AVX512VL

Instruction(s): vpandnq

Compute the bitwise AND NOT of packed 64-bit integers in a and b, and return the results using writemask k (elements are copied from src when the corresponding mask bit is not set).

_mm_maskz_andnot_epi64

    __m128i _mm_maskz_andnot_epi64(__mmask8 k, __m128i a, __m128i b)

CPUID Flags: AVX512F, AVX512VL

Instruction(s): vpandnq

Compute the bitwise AND NOT of packed 64-bit integers in a and b, and return the results using zeromask k (elements are zeroed out when the corresponding mask bit is not set).

_mm256_mask_andnot_epi64

    __m256i _mm256_mask_andnot_epi64(__m256i src, __mmask8 k, __m256i a, __m256i b)

CPUID Flags: AVX512F, AVX512VL

Instruction(s): vpandnq

Compute the bitwise AND NOT of packed 64-bit integers in a and b, and return the results using writemask k (elements are copied from src when the corresponding mask bit is not set).

_mm256_maskz_andnot_epi64

    __m256i _mm256_maskz_andnot_epi64(__mmask8 k, __m256i a, __m256i b)

CPUID Flags: AVX512F, AVX512VL

Instruction(s): vpandnq

Compute the bitwise AND NOT of packed 64-bit integers in a and b, and return the results using zeromask k (elements are zeroed out when the corresponding mask bit is not set).

_mm_mask_and_epi64

    __m128i _mm_mask_and_epi64(__m128i src, __mmask8 k, __m128i a, __m128i b)

CPUID Flags: AVX512F, AVX512VL

Instruction(s): vpandq

Compute the bitwise AND of packed 64-bit integers in a and b, and return the results using writemask k (elements are copied from src when the corresponding mask bit is not set).

_mm_maskz_and_epi64

    __m128i _mm_maskz_and_epi64(__mmask8 k, __m128i a, __m128i b)

CPUID Flags: AVX512F, AVX512VL

Instruction(s): vpandq

Compute the bitwise AND of packed 64-bit integers in a and b, and return the results using zeromask k (elements are zeroed out when the corresponding mask bit is not set).

_mm256_mask_and_epi64

    __m256i _mm256_mask_and_epi64(__m256i src, __mmask8 k, __m256i a, __m256i b)

CPUID Flags: AVX512F, AVX512VL

Instruction(s): vpandq

Compute the bitwise AND of packed 64-bit integers in a and b, and return the results using writemask k (elements are copied from src when the corresponding mask bit is not set).

_mm256_maskz_and_epi64

    __m256i _mm256_maskz_and_epi64(__mmask8 k, __m256i a, __m256i b)

CPUID Flags: AVX512F, AVX512VL

Instruction(s): vpandq

Compute the bitwise AND of packed 64-bit integers in a and b, and return the results using zeromask k (elements are zeroed out when the corresponding mask bit is not set).

_mm_mask_or_epi32

    __m128i _mm_mask_or_epi32(__m128i src, __mmask8 k, __m128i a, __m128i b)

CPUID Flags: AVX512F, AVX512VL

Instruction(s): vpord

Compute the bitwise OR of packed 32-bit integers in a and b, and return the results using writemask k (elements are copied from src when the corresponding mask bit is not set).

_mm_maskz_or_epi32

    __m128i _mm_maskz_or_epi32(__mmask8 k, __m128i a, __m128i b)

CPUID Flags: AVX512F, AVX512VL

Instruction(s): vpord

Compute the bitwise OR of packed 32-bit integers in a and b, and return the results using zeromask k (elements are zeroed out when the corresponding mask bit is not set).

_mm256_mask_or_epi32

    __m256i _mm256_mask_or_epi32(__m256i src, __mmask8 k, __m256i a, __m256i b)

CPUID Flags: AVX512F, AVX512VL

Instruction(s): vpord

Compute the bitwise OR of packed 32-bit integers in a and b, and return the results using writemask k (elements are copied from src when the corresponding mask bit is not set).

_mm256_maskz_or_epi32

    __m256i _mm256_maskz_or_epi32(__mmask8 k, __m256i a, __m256i b)

CPUID Flags: AVX512F, AVX512VL

Instruction(s): vpord

Compute the bitwise OR of packed 32-bit integers in a and b, and return the results using zeromask k (elements are zeroed out when the corresponding mask bit is not set).

_mm_mask_or_epi64

    __m128i _mm_mask_or_epi64(__m128i src, __mmask8 k, __m128i a, __m128i b)

CPUID Flags: AVX512F, AVX512VL

Instruction(s): vporq

Compute the bitwise OR of packed 64-bit integers in a and b, and return the results using writemask k (elements are copied from src when the corresponding mask bit is not set).

_mm_maskz_or_epi64

    __m128i _mm_maskz_or_epi64(__mmask8 k, __m128i a, __m128i b)

CPUID Flags: AVX512F, AVX512VL

Instruction(s): vporq

Compute the bitwise OR of packed 64-bit integers in a and b, and return the results using zeromask k (elements are zeroed out when the corresponding mask bit is not set).

_mm256_mask_or_epi64

    __m256i _mm256_mask_or_epi64(__m256i src, __mmask8 k, __m256i a, __m256i b)

CPUID Flags: AVX512F, AVX512VL

Instruction(s): vporq

Compute the bitwise OR of packed 64-bit integers in a and b, and return the results using writemask k (elements are copied from src when the corresponding mask bit is not set).

_mm256_maskz_or_epi64

    __m256i _mm256_maskz_or_epi64(__mmask8 k, __m256i a, __m256i b)

CPUID Flags: AVX512F, AVX512VL

Instruction(s): vporq

Compute the bitwise OR of packed 64-bit integers in a and b, and return the results using zeromask k (elements are zeroed out when the corresponding mask bit is not set).

_mm_mask_ternarylogic_epi32

    __m128i _mm_mask_ternarylogic_epi32(__m128i src, __mmask8 k, __m128i a, __m128i b, int imm8)

CPUID Flags: AVX512F, AVX512VL

Instruction(s): vpternlogd

Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in imm8. For each bit in each packed 32-bit integer, the corresponding bit from src, a, and b are used to form a 3 bit index into imm8, and the value at that bit in imm8 is written to the corresponding bit in the return value using writemask k at 32-bit granularity (32-bit elements are copied from src when the corresponding mask bit is not set).

_mm_maskz_ternarylogic_epi32

    __m128i _mm_maskz_ternarylogic_epi32(__mmask8 k, __m128i a, __m128i b, __m128i c, int imm8)

CPUID Flags: AVX512F, AVX512VL

Instruction(s): vpternlogd

Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in imm8. For each bit in each packed 32-bit integer, the corresponding bit from a, b, and c are used to form a 3 bit index into imm8, and the value at that bit in imm8 is written to the corresponding bit in the return value using zeromask k at 32-bit granularity (32-bit elements are zeroed out when the corresponding mask bit is not set).

_mm_ternarylogic_epi32

    __m128i _mm_ternarylogic_epi32(__m128i a, __m128i b, __m128i c, int imm8)

CPUID Flags: AVX512F, AVX512VL

Instruction(s): vpternlogd

Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in imm8. For each bit in each packed 32-bit integer, the corresponding bit from a, b, and c are used to form a 3 bit index into imm8, and the value at that bit in imm8 is written to the corresponding bit in the return value.

_mm256_mask_ternarylogic_epi32

    __m256i _mm256_mask_ternarylogic_epi32(__m256i src, __mmask8 k, __m256i a, __m256i b, int imm8)

CPUID Flags: AVX512F, AVX512VL

Instruction(s): vpternlogd

Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in imm8. For each bit in each packed 32-bit integer, the corresponding bit from src, a, and b are used to form a 3 bit index into imm8, and the value at that bit in imm8 is written to the corresponding bit in the return value using writemask k at 32-bit granularity (32-bit elements are copied from src when the corresponding mask bit is not set).

_mm256_maskz_ternarylogic_epi32

    __m256i _mm256_maskz_ternarylogic_epi32(__mmask8 k, __m256i a, __m256i b, __m256i c, int imm8)

CPUID Flags: AVX512F, AVX512VL

Instruction(s): vpternlogd

Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in imm8. For each bit in each packed 32-bit integer, the corresponding bit from a, b, and c are used to form a 3 bit index into imm8, and the value at that bit in imm8 is written to the corresponding bit in the return value using zeromask k at 32-bit granularity (32-bit elements are zeroed out when the corresponding mask bit is not set).

_mm256_ternarylogic_epi32

    __m256i _mm256_ternarylogic_epi32(__m256i a, __m256i b, __m256i c, int imm8)

CPUID Flags: AVX512F, AVX512VL

Instruction(s): vpternlogd

Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in imm8. For each bit in each packed 32-bit integer, the corresponding bit from a, b, and c are used to form a 3 bit index into imm8, and the value at that bit in imm8 is written to the corresponding bit in the return value.

_mm_mask_ternarylogic_epi64

    __m128i _mm_mask_ternarylogic_epi64(__m128i src, __mmask8 k, __m128i a, __m128i b, int imm8)

CPUID Flags: AVX512F, AVX512VL

Instruction(s): vpternlogq

Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in imm8. For each bit in each packed 64-bit integer, the corresponding bit from src, a, and b are used to form a 3 bit index into imm8, and the value at that bit in imm8 is written to the corresponding bit in the return value using writemask k at 64-bit granularity (64-bit elements are copied from src when the corresponding mask bit is not set).

_mm_maskz_ternarylogic_epi64

    __m128i _mm_maskz_ternarylogic_epi64(__mmask8 k, __m128i a, __m128i b, __m128i c, int imm8)

CPUID Flags: AVX512F, AVX512VL

Instruction(s): vpternlogq

Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in imm8. For each bit in each packed 64-bit integer, the corresponding bit from a, b, and c are used to form a 3 bit index into imm8, and the value at that bit in imm8 is written to the corresponding bit in the return value using zeromask k at 64-bit granularity (64-bit elements are zeroed out when the corresponding mask bit is not set).

_mm_ternarylogic_epi64

    __m128i _mm_ternarylogic_epi64(__m128i a, __m128i b, __m128i c, int imm8)

CPUID Flags: AVX512F, AVX512VL

Instruction(s): vpternlogq

Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in imm8. For each bit in each packed 64-bit integer, the corresponding bit from a, b, and c are used to form a 3 bit index into imm8, and the value at that bit in imm8 is written to the corresponding bit in the return value.

_mm256_mask_ternarylogic_epi64

    __m256i _mm256_mask_ternarylogic_epi64(__m256i src, __mmask8 k, __m256i a, __m256i b, int imm8)

CPUID Flags: AVX512F, AVX512VL

Instruction(s): vpternlogq

Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in imm8. For each bit in each packed 64-bit integer, the corresponding bit from src, a, and b are used to form a 3 bit index into imm8, and the value at that bit in imm8 is written to the corresponding bit in the return value using writemask k at 64-bit granularity (64-bit elements are copied from src when the corresponding mask bit is not set).

_mm256_maskz_ternarylogic_epi64

    __m256i _mm256_maskz_ternarylogic_epi64(__mmask8 k, __m256i a, __m256i b, __m256i c, int imm8)

CPUID Flags: AVX512F, AVX512VL

Instruction(s): vpternlogq

Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in imm8. For each bit in each packed 64-bit integer, the corresponding bit from a, b, and c are used to form a 3 bit index into imm8, and the value at that bit in imm8 is written to the corresponding bit in the return value using zeromask k at 64-bit granularity (64-bit elements are zeroed out when the corresponding mask bit is not set).

_mm256_ternarylogic_epi64

    __m256i _mm256_ternarylogic_epi64(__m256i a, __m256i b, __m256i c, int imm8)

CPUID Flags: AVX512F, AVX512VL

Instruction(s): vpternlogq

Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in imm8. For each bit in each packed 64-bit integer, the corresponding bit from a, b, and c are used to form a 3 bit index into imm8, and the value at that bit in imm8 is written to the corresponding bit in the return value.

_mm_mask_xor_epi32

    __m128i _mm_mask_xor_epi32(__m128i src, __mmask8 k, __m128i a, __m128i b)

CPUID Flags: AVX512F, AVX512VL

Instruction(s): vpxord

Compute the bitwise XOR of packed 32-bit integers in a and b, and return the results using writemask k (elements are copied from src when the corresponding mask bit is not set).

_mm_maskz_xor_epi32

    __m128i _mm_maskz_xor_epi32(__mmask8 k, __m128i a, __m128i b)

CPUID Flags: AVX512F, AVX512VL

Instruction(s): vpxord

Compute the bitwise XOR of packed 32-bit integers in a and b, and return the results using zeromask k (elements are zeroed out when the corresponding mask bit is not set).

_mm256_mask_xor_epi32

    __m256i _mm256_mask_xor_epi32(__m256i src, __mmask8 k, __m256i a, __m256i b)

CPUID Flags: AVX512F, AVX512VL

Instruction(s): vpxord

Compute the bitwise XOR of packed 32-bit integers in a and b, and return the results using writemask k (elements are copied from src when the corresponding mask bit is not set).

_mm256_maskz_xor_epi32

    __m256i _mm256_maskz_xor_epi32(__mmask8 k, __m256i a, __m256i b)

CPUID Flags: AVX512F, AVX512VL

Instruction(s): vpxord

Compute the bitwise XOR of packed 32-bit integers in a and b, and return the results using zeromask k (elements are zeroed out when the corresponding mask bit is not set).

_mm_mask_xor_epi64

    __m128i _mm_mask_xor_epi64(__m128i src, __mmask8 k, __m128i a, __m128i b)

CPUID Flags: AVX512F, AVX512VL

Instruction(s): vpxorq

Compute the bitwise XOR of packed 64-bit integers in a and b, and return the results using writemask k (elements are copied from src when the corresponding mask bit is not set).

_mm_maskz_xor_epi64

    __m128i _mm_maskz_xor_epi64(__mmask8 k, __m128i a, __m128i b)

CPUID Flags: AVX512F, AVX512VL

Instruction(s): vpxorq

Compute the bitwise XOR of packed 64-bit integers in a and b, and return the results using zeromask k (elements are zeroed out when the corresponding mask bit is not set).

_mm256_mask_xor_epi64

    __m256i _mm256_mask_xor_epi64(__m256i src, __mmask8 k, __m256i a, __m256i b)

CPUID Flags: AVX512F, AVX512VL

Instruction(s): vpxorq

Compute the bitwise XOR of packed 64-bit integers in a and b, and return the results using writemask k (elements are copied from src when the corresponding mask bit is not set).

_mm256_maskz_xor_epi64

    __m256i _mm256_maskz_xor_epi64(__mmask8 k, __m256i a, __m256i b)

CPUID Flags: AVX512F, AVX512VL

Instruction(s): vpxorq

Compute the bitwise XOR of packed 64-bit integers in a and b, and return the results using zeromask k (elements are zeroed out when the corresponding mask bit is not set).

Parent topic: Intrinsics for Intel® Advanced Vector Extensions 512 (Intel® AVX-512) Additional Instructions