# _mm256_srl_epi16/32/64

Logical shift of word/doubleword/quadword elements to right according to specified number. The corresponding Intel® AVX2 instruction is `VPSRLW`, `VPSRLD`, or `VPSRLQ`.

## Syntax

extern __m256i _mm256_srl_epi16(__m256i s1, __m128i count);

extern __m256i _mm256_srl_epi32(__m256i s1, __m128i count);

extern __m256i _mm256_srl_epi64(__m256i s1, __m128i count);

## Arguments

s1 | integer source vector used for the operation
count | 128-bit memory location used for the operation

## Description

Performs a logical shift of the bits in the individual data elements (16-bit word, 32-bit doubleword, or 64-bit quadword) in source vector s1 to the right by the number of bits specified in count. The empty low-order bytes are cleared (set to all '0'). If the value specified by count is greater than 15/31/63 (depending on the intrinsic being used), the destination vector is set to all '0'.

The count argument is a 128-bit memory location. Note that only the first 64-bits of a 128-bit count operand are checked to compute the count.

## Returns

Result of the right-shift operation.

Parent topic: Intrinsics for Logical Shift Operations