# _mm256_testnzc_pd, _mm_testnzc_pd

Performs a packed bit test of two 256-bit float64 or 128-bit float64 vectors to check ZF and CF flag settings. The corresponding Intel® AVX instruction is VTESTPD.

## Syntax

extern int _mm256_testnzc_pd(__m256d s1, __m256d s2);

extern int _mm_testnzc_pd(__m128d s1, __m256d s2);

## Arguments

s1 | first source float64 vector
s2 | second source float64 vector

## Description

Performs a packed bit test of s1 and s2 vectors using VTESTPD s1, s2 instruction and checks the status of the ZF and CF flags. The intrinsic returns 1 if both ZF and CF flags are not 1 (that is, both flags are not set), otherwise returns 0 (that is, one of the flags is set).

The VTESTPD instruction performs a bitwise comparison of all the sign bits of the double-precision elements in the first source operand and corresponding sign bits in the second source operand. If the AND of the first source operand sign bits with the second source operand sign bits produces all zeros, the ZF flag is set else the ZF flag is clear. If the AND of the inverted first source operand sign bits with the second source operand sign bits produces all zeros the CF flag is set, else the CF flag is clear.

The _mm_testnzc_pd intrinsic checks the ZF and CF flags according to results of the 128-bit float64 source vectors. The _m256_testnzc_pd intrinsic checks the ZF and CF flags according to the results of the 256-bit float64 source vectors.

### Note

Intel® Advanced Vector Extensions (Intel® AVX) instructions include a full compliment of 128-bit SIMD instructions. Such Intel® AVX instructions, with vector length of 128-bits, zeroes the upper 128 bits of the YMM register. The lower 128 bits of the YMM register is aliased to the corresponding SIMD XMM register.

## Returns

1: indicates that both ZF and CF flags are clear

0: indicates that either ZF or CF flag is set

Parent topic: Intrinsics for Packed Test Operations