| setting_showUnpublishedSettings |
false |
| setting_showInternalSettings |
false |
| setting_preciseIllegalMemAccessException |
false |
| io_regionbase |
0 |
| io_regionsize |
0 |
| setting_support31bitdcachebypass |
true |
| setting_activateTrace |
false |
| mpu_useLimit |
false |
| mpu_enabled |
false |
| mmu_enabled |
false |
| mmu_autoAssignTlbPtrSz |
true |
| cpuReset |
false |
| resetrequest_enabled |
true |
| setting_shadowRegisterSets |
0 |
| mpu_numOfInstRegion |
8 |
| mpu_numOfDataRegion |
8 |
| mmu_TLBMissExcOffset |
0 |
| resetOffset |
0 |
| exceptionOffset |
32 |
| cpuID |
0 |
| resetSlave |
onchip_memory2_0.s1 |
| mmu_TLBMissExcSlave |
None |
| exceptionSlave |
onchip_memory2_0.s1 |
| setting_interruptControllerType |
Internal |
| setting_branchpredictiontype |
Dynamic |
| setting_bhtPtrSz |
8 |
| mul_shift_choice |
0 |
| mul_32_impl |
2 |
| mul_64_impl |
0 |
| shift_rot_impl |
1 |
| dividerType |
no_div |
| mpu_minInstRegionSize |
12 |
| mpu_minDataRegionSize |
12 |
| mmu_uitlbNumEntries |
4 |
| mmu_udtlbNumEntries |
6 |
| mmu_tlbPtrSz |
7 |
| mmu_tlbNumWays |
16 |
| mmu_processIDNumBits |
8 |
| impl |
Fast |
| icache_size |
2048 |
| fa_cache_line |
2 |
| fa_cache_linesize |
0 |
| icache_numTCIM |
0 |
| icache_burstType |
None |
| dcache_bursts |
false |
| dcache_victim_buf_impl |
ram |
| dcache_size |
2048 |
| dcache_numTCDM |
0 |
| setting_ecc_present |
false |
| debug_enabled |
true |
| debug_debugReqSignals |
false |
| debug_OCIOnchipTrace |
_128 |
| debug_hwbreakpoint |
0 |
| debug_datatrigger |
0 |
| debug_traceType |
none |
| debug_traceStorage |
onchip_trace |
| resetAbsoluteAddr |
0 |
| exceptionAbsoluteAddr |
32 |
| mmu_TLBMissExcAbsAddr |
0 |
| deviceFamily |
UNKNOWN |
| generateLegacySim |
false |