msgdma |
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2019.03.15.18:41:43 | Datasheet |
cpu | msgdma_m2m_stride | |||
data_master | instruction_master | mm_read | mm_write | |
cpu | ||||
debug_mem_slave | 0x00080800 | 0x00080800 | ||
jtag_uart_0 | ||||
avalon_jtag_slave | 0x000810a8 | |||
msgdma_m2m_stride | ||||
csr | 0x00081080 | |||
descriptor_slave | 0x00081060 | |||
onchip_memory2_0 | ||||
s1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 |
performance_counter_0 | ||||
control_slave | 0x00081000 | |||
sysid_qsys_0 | ||||
control_slave | 0x000810a0 | |||
timer_0 | ||||
s1 | 0x00081040 |
Parameters
|
Software Assignments(none) |
clock_in | out_clk | cpu | |
clk | |||
reset_in | out_reset | ||
reset | |||
data_master | jtag_uart_0 | ||
avalon_jtag_slave | |||
irq | |||
irq | |||
debug_reset_request | |||
reset | |||
data_master | performance_counter_0 | ||
control_slave | |||
debug_reset_request | |||
reset | |||
data_master | sysid_qsys_0 | ||
control_slave | |||
debug_reset_request | |||
reset | |||
data_master | msgdma_m2m_stride | ||
csr | |||
data_master | |||
descriptor_slave | |||
irq | |||
csr_irq | |||
debug_reset_request | |||
reset_n | |||
data_master | onchip_memory2_0 | ||
s1 | |||
instruction_master | |||
s1 | |||
debug_reset_request | |||
reset1 | |||
data_master | timer_0 | ||
s1 | |||
irq | |||
irq | |||
debug_reset_request | |||
reset | |||
debug_reset_request | iopll_0 | ||
reset |
Parameters
|
Software Assignments
|
clock_in | out_clk | iopll_0 | |
refclk | |||
cpu | debug_reset_request | ||
reset | |||
outclk0 | msgdma_m2m_stride | ||
clock |
Parameters
|
Software Assignments(none) |
cpu | data_master | jtag_uart_0 |
avalon_jtag_slave | ||
irq | ||
irq | ||
debug_reset_request | ||
reset | ||
clock_in | out_clk | |
clk |
Parameters
|
Software Assignments
|
cpu | data_master | msgdma_m2m_stride | |
csr | |||
data_master | |||
descriptor_slave | |||
irq | |||
csr_irq | |||
debug_reset_request | |||
reset_n | |||
iopll_0 | outclk0 | ||
clock | |||
reset_in | out_reset | ||
reset_n | |||
mm_read | onchip_memory2_0 | ||
s1 | |||
mm_write | |||
s1 |
Parameters
|
Software Assignments
|
cpu | data_master | onchip_memory2_0 |
s1 | ||
instruction_master | ||
s1 | ||
debug_reset_request | ||
reset1 | ||
msgdma_m2m_stride | mm_read | |
s1 | ||
mm_write | ||
s1 | ||
clock_in | out_clk | |
clk1 | ||
reset_in | out_reset | |
reset1 |
Parameters
|
Software Assignments
|
cpu | data_master | performance_counter_0 |
control_slave | ||
debug_reset_request | ||
reset | ||
clock_in | out_clk | |
clk | ||
reset_in | out_reset | |
reset |
Parameters
|
Software Assignments
|
clock_in | out_clk | reset_in | |
clk | |||
out_reset | performance_counter_0 | ||
reset | |||
out_reset | sysid_qsys_0 | ||
reset | |||
out_reset | timer_0 | ||
reset | |||
out_reset | cpu | ||
reset | |||
out_reset | onchip_memory2_0 | ||
reset1 | |||
out_reset | msgdma_m2m_stride | ||
reset_n |
Parameters
|
Software Assignments(none) |
cpu | data_master | sysid_qsys_0 |
control_slave | ||
debug_reset_request | ||
reset | ||
clock_in | out_clk | |
clk | ||
reset_in | out_reset | |
reset |
Parameters
|
Software Assignments
|
cpu | data_master | timer_0 |
s1 | ||
irq | ||
irq | ||
debug_reset_request | ||
reset | ||
clock_in | out_clk | |
clk | ||
reset_in | out_reset | |
reset |
Parameters
|
Software Assignments
|
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