msgdma

2019.03.15.18:41:43 Datasheet
Overview
Processor
   cpu Nios II 18.1
All Components
   cpu altera_nios2_gen2 18.1
   jtag_uart_0 altera_avalon_jtag_uart 18.1
   msgdma_m2m_stride altera_msgdma 18.1
   onchip_memory2_0 altera_avalon_onchip_memory2 18.1
   performance_counter_0 altera_avalon_performance_counter 18.1
   sysid_qsys_0 altera_avalon_sysid_qsys 18.1
   timer_0 altera_avalon_timer 18.1
Memory Map
cpu msgdma_m2m_stride
 data_master  instruction_master  mm_read  mm_write
  cpu
debug_mem_slave  0x00080800 0x00080800
  jtag_uart_0
avalon_jtag_slave  0x000810a8
  msgdma_m2m_stride
csr  0x00081080
descriptor_slave  0x00081060
  onchip_memory2_0
s1  0x00000000 0x00000000 0x00000000 0x00000000
  performance_counter_0
control_slave  0x00081000
  sysid_qsys_0
control_slave  0x000810a0
  timer_0
s1  0x00081040

clock_in

altera_clock_bridge v18.1


Parameters

generateLegacySim false
  

Software Assignments

(none)

cpu

altera_nios2_gen2 v18.1
clock_in out_clk   cpu
  clk
reset_in out_reset  
  reset
data_master   jtag_uart_0
  avalon_jtag_slave
irq  
  irq
debug_reset_request  
  reset
data_master   performance_counter_0
  control_slave
debug_reset_request  
  reset
data_master   sysid_qsys_0
  control_slave
debug_reset_request  
  reset
data_master   msgdma_m2m_stride
  csr
data_master  
  descriptor_slave
irq  
  csr_irq
debug_reset_request  
  reset_n
data_master   onchip_memory2_0
  s1
instruction_master  
  s1
debug_reset_request  
  reset1
data_master   timer_0
  s1
irq  
  irq
debug_reset_request  
  reset
debug_reset_request   iopll_0
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIG_ENDIAN 0
BREAK_ADDR 0x00080820
CPU_ARCH_NIOS2_R1
CPU_FREQ 100000000u
CPU_ID_SIZE 1
CPU_ID_VALUE 0x00000000
CPU_IMPLEMENTATION "fast"
DATA_ADDR_WIDTH 20
DCACHE_BYPASS_MASK 0x80000000
DCACHE_LINE_SIZE 32
DCACHE_LINE_SIZE_LOG2 5
DCACHE_SIZE 2048
EXCEPTION_ADDR 0x00000020
FLASH_ACCELERATOR_LINES 0
FLASH_ACCELERATOR_LINE_SIZE 0
FLUSHDA_SUPPORTED
HARDWARE_DIVIDE_PRESENT 0
HARDWARE_MULTIPLY_PRESENT 1
HARDWARE_MULX_PRESENT 0
HAS_DEBUG_CORE 1
HAS_DEBUG_STUB
HAS_EXTRA_EXCEPTION_INFO
HAS_ILLEGAL_INSTRUCTION_EXCEPTION
HAS_JMPI_INSTRUCTION
ICACHE_LINE_SIZE 32
ICACHE_LINE_SIZE_LOG2 5
ICACHE_SIZE 2048
INITDA_SUPPORTED
INST_ADDR_WIDTH 20
NUM_OF_SHADOW_REG_SETS 0
OCI_VERSION 1
RESET_ADDR 0x00000000

iopll_0

altera_iopll v18.1
clock_in out_clk   iopll_0
  refclk
cpu debug_reset_request  
  reset
outclk0   msgdma_m2m_stride
  clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

jtag_uart_0

altera_avalon_jtag_uart v18.1
cpu data_master   jtag_uart_0
  avalon_jtag_slave
irq  
  irq
debug_reset_request  
  reset
clock_in out_clk  
  clk


Parameters

generateLegacySim false
  

Software Assignments

READ_DEPTH 64
READ_THRESHOLD 8
WRITE_DEPTH 64
WRITE_THRESHOLD 8

msgdma_m2m_stride

altera_msgdma v18.1
cpu data_master   msgdma_m2m_stride
  csr
data_master  
  descriptor_slave
irq  
  csr_irq
debug_reset_request  
  reset_n
iopll_0 outclk0  
  clock
reset_in out_reset  
  reset_n
mm_read   onchip_memory2_0
  s1
mm_write  
  s1


Parameters

generateLegacySim false
  

Software Assignments

BURST_ENABLE 0
BURST_WRAPPING_SUPPORT 0
CHANNEL_ENABLE 0
CHANNEL_ENABLE_DERIVED 0
CHANNEL_WIDTH 8
DATA_FIFO_DEPTH 32
DATA_WIDTH 32
DESCRIPTOR_FIFO_DEPTH 128
DMA_MODE 0
ENHANCED_FEATURES 1
ERROR_ENABLE 0
ERROR_ENABLE_DERIVED 0
ERROR_WIDTH 8
MAX_BURST_COUNT 2
MAX_BYTE 2048
MAX_STRIDE 2
PACKET_ENABLE 0
PACKET_ENABLE_DERIVED 0
PREFETCHER_ENABLE 0
PROGRAMMABLE_BURST_ENABLE 0
RESPONSE_PORT 2
STRIDE_ENABLE 1
STRIDE_ENABLE_DERIVED 1
TRANSFER_TYPE Aligned Accesses

onchip_memory2_0

altera_avalon_onchip_memory2 v18.1
cpu data_master   onchip_memory2_0
  s1
instruction_master  
  s1
debug_reset_request  
  reset1
msgdma_m2m_stride mm_read  
  s1
mm_write  
  s1
clock_in out_clk  
  clk1
reset_in out_reset  
  reset1


Parameters

generateLegacySim false
  

Software Assignments

ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
CONTENTS_INFO ""
DUAL_PORT 0
GUI_RAM_BLOCK_TYPE AUTO
INIT_CONTENTS_FILE msgdma_onchip_memory2_0_onchip_memory2_0
INIT_MEM_CONTENT 1
INSTANCE_ID NONE
NON_DEFAULT_INIT_FILE_ENABLED 0
RAM_BLOCK_TYPE AUTO
READ_DURING_WRITE_MODE DONT_CARE
SINGLE_CLOCK_OP 0
SIZE_MULTIPLE 1
SIZE_VALUE 524288
WRITABLE 1

performance_counter_0

altera_avalon_performance_counter v18.1
cpu data_master   performance_counter_0
  control_slave
debug_reset_request  
  reset
clock_in out_clk  
  clk
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

HOW_MANY_SECTIONS 3

reset_in

altera_reset_bridge v18.1
clock_in out_clk   reset_in
  clk
out_reset   performance_counter_0
  reset
out_reset   sysid_qsys_0
  reset
out_reset   timer_0
  reset
out_reset   cpu
  reset
out_reset   onchip_memory2_0
  reset1
out_reset   msgdma_m2m_stride
  reset_n


Parameters

generateLegacySim false
  

Software Assignments

(none)

sysid_qsys_0

altera_avalon_sysid_qsys v18.1
cpu data_master   sysid_qsys_0
  control_slave
debug_reset_request  
  reset
clock_in out_clk  
  clk
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

ID 10
TIMESTAMP 0

timer_0

altera_avalon_timer v18.1
cpu data_master   timer_0
  s1
irq  
  irq
debug_reset_request  
  reset
clock_in out_clk  
  clk
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

ALWAYS_RUN 0
COUNTER_SIZE 32
FIXED_PERIOD 0
FREQ 100000000
LOAD_VALUE 999999
MULT 0.001
PERIOD 10
PERIOD_UNITS ms
RESET_OUTPUT 0
SNAPSHOT 1
TICKS_PER_SEC 100
TIMEOUT_PULSE_OUTPUT 0
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