| Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
| custom_reconfig_master_inst|mgmt_cpu_inst |
103 |
0 |
0 |
0 |
92 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| custom_reconfig_master_inst |
67 |
55 |
0 |
55 |
81 |
55 |
55 |
55 |
0 |
0 |
0 |
0 |
0 |
| custom_phy_master_inst2|mgmt_cpu_inst |
72 |
0 |
0 |
0 |
79 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| custom_phy_master_inst2 |
36 |
22 |
0 |
22 |
67 |
22 |
22 |
22 |
0 |
0 |
0 |
0 |
0 |
| custom_phy_master_inst1|mgmt_cpu_inst |
72 |
0 |
0 |
0 |
79 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| custom_phy_master_inst1 |
36 |
22 |
0 |
22 |
67 |
22 |
22 |
22 |
0 |
0 |
0 |
0 |
0 |
| prbs_checker_x4_inst_normal|prbs_checker_inst_lane4|atso_prbs_poly_inst|atso_poly_inst |
18 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| prbs_checker_x4_inst_normal|prbs_checker_inst_lane4|atso_prbs_poly_inst |
19 |
1 |
0 |
1 |
16 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| prbs_checker_x4_inst_normal|prbs_checker_inst_lane4 |
19 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| prbs_checker_x4_inst_normal|prbs_checker_inst_lane3|atso_prbs_poly_inst|atso_poly_inst |
18 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| prbs_checker_x4_inst_normal|prbs_checker_inst_lane3|atso_prbs_poly_inst |
19 |
1 |
0 |
1 |
16 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| prbs_checker_x4_inst_normal|prbs_checker_inst_lane3 |
19 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| prbs_checker_x4_inst_normal|prbs_checker_inst_lane2|atso_prbs_poly_inst|atso_poly_inst |
18 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| prbs_checker_x4_inst_normal|prbs_checker_inst_lane2|atso_prbs_poly_inst |
19 |
1 |
0 |
1 |
16 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| prbs_checker_x4_inst_normal|prbs_checker_inst_lane2 |
19 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| prbs_checker_x4_inst_normal|prbs_checker_inst_lane1|atso_prbs_poly_inst|atso_poly_inst |
18 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| prbs_checker_x4_inst_normal|prbs_checker_inst_lane1|atso_prbs_poly_inst |
19 |
1 |
0 |
1 |
16 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| prbs_checker_x4_inst_normal|prbs_checker_inst_lane1 |
19 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| prbs_checker_x4_inst_normal |
35 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| prbs_gen_inst|atso_prbs_poly_inst|atso_poly_inst |
18 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| prbs_gen_inst|atso_prbs_poly_inst |
19 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| prbs_gen_inst |
5 |
3 |
0 |
3 |
16 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| syncgen_16bit_4lanes_inst|p4 |
18 |
3 |
12 |
3 |
18 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| syncgen_16bit_4lanes_inst|p3 |
18 |
3 |
12 |
3 |
18 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| syncgen_16bit_4lanes_inst|p2 |
18 |
3 |
12 |
3 |
18 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| syncgen_16bit_4lanes_inst|p1 |
18 |
3 |
12 |
3 |
18 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| syncgen_16bit_4lanes_inst |
15 |
0 |
0 |
0 |
72 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| datagen_controller_inst |
4 |
12 |
1 |
12 |
13 |
12 |
12 |
12 |
0 |
0 |
0 |
0 |
0 |
| gxb_state_mc_inst |
6 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|basic|s5|bundle |
371 |
84 |
24 |
84 |
440 |
84 |
84 |
84 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|basic|s5|pif[3].pif_arb |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|basic|s5|pif[2].pif_arb |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|basic|s5|pif[1].pif_arb |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|basic|s5|pif[0].pif_arb |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|basic|s5|lif[0].logical_if|pif_tbus_mux |
27 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|basic|s5|lif[0].logical_if|lif_csr|l2paddr |
16 |
0 |
0 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|basic|s5|lif[0].logical_if|lif_csr|l2pch |
8 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|basic|s5|lif[0].logical_if|lif_csr |
57 |
0 |
0 |
0 |
94 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|basic|s5|lif[0].logical_if |
204 |
0 |
0 |
0 |
237 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|basic|s5 |
227 |
0 |
0 |
0 |
346 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|basic |
227 |
1 |
0 |
1 |
347 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|cal_seq |
13 |
5 |
0 |
5 |
14 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|altera_wait_generate_inst|rst_sync |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|altera_wait_generate_inst |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_ram_inst|altsyncram_component|auto_generated |
96 |
0 |
0 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_ram_inst |
96 |
4 |
0 |
4 |
64 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_inst|rst_controller|alt_rst_req_sync_uq1 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_inst|rst_controller|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_inst|rst_controller |
33 |
31 |
0 |
31 |
2 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_inst|irq_mapper |
3 |
31 |
2 |
31 |
32 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_inst|mm_interconnect_0|rsp_xbar_mux_001 |
94 |
0 |
2 |
0 |
92 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_inst|mm_interconnect_0|rsp_xbar_mux|arb|adder |
8 |
4 |
0 |
4 |
4 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_inst|mm_interconnect_0|rsp_xbar_mux|arb |
6 |
0 |
4 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_inst|mm_interconnect_0|rsp_xbar_mux |
185 |
0 |
0 |
0 |
93 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_inst|mm_interconnect_0|rsp_xbar_demux_001 |
94 |
1 |
2 |
1 |
92 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_inst|mm_interconnect_0|rsp_xbar_demux |
95 |
4 |
2 |
4 |
183 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_inst|mm_interconnect_0|cmd_xbar_mux_001 |
94 |
0 |
2 |
0 |
92 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_inst|mm_interconnect_0|cmd_xbar_mux|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_inst|mm_interconnect_0|cmd_xbar_mux|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_inst|mm_interconnect_0|cmd_xbar_mux |
185 |
0 |
0 |
0 |
93 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_inst|mm_interconnect_0|cmd_xbar_demux_001 |
94 |
1 |
2 |
1 |
92 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_inst|mm_interconnect_0|cmd_xbar_demux |
95 |
4 |
2 |
4 |
183 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_inst|mm_interconnect_0|id_router_001|the_default_decode |
0 |
2 |
0 |
2 |
2 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_inst|mm_interconnect_0|id_router_001 |
92 |
0 |
2 |
0 |
92 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_inst|mm_interconnect_0|id_router|the_default_decode |
0 |
2 |
0 |
2 |
2 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_inst|mm_interconnect_0|id_router |
92 |
0 |
2 |
0 |
92 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_inst|mm_interconnect_0|addr_router_001|the_default_decode |
0 |
3 |
0 |
3 |
3 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_inst|mm_interconnect_0|addr_router_001 |
92 |
3 |
3 |
3 |
92 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_inst|mm_interconnect_0|addr_router|the_default_decode |
0 |
3 |
0 |
3 |
3 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_inst|mm_interconnect_0|addr_router |
92 |
0 |
3 |
0 |
92 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_inst|mm_interconnect_0|reconfig_ctrl_ctrl_translator_avalon_universal_slave_0_agent_rsp_fifo |
132 |
39 |
0 |
39 |
91 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_inst|mm_interconnect_0|reconfig_ctrl_ctrl_translator_avalon_universal_slave_0_agent|uncompressor |
30 |
1 |
0 |
1 |
28 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_inst|mm_interconnect_0|reconfig_ctrl_ctrl_translator_avalon_universal_slave_0_agent |
258 |
39 |
39 |
39 |
274 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_inst|mm_interconnect_0|reconfig_mem_mem_translator_avalon_universal_slave_0_agent_rsp_fifo |
132 |
39 |
0 |
39 |
91 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_inst|mm_interconnect_0|reconfig_mem_mem_translator_avalon_universal_slave_0_agent|uncompressor |
30 |
1 |
0 |
1 |
28 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_inst|mm_interconnect_0|reconfig_mem_mem_translator_avalon_universal_slave_0_agent |
258 |
39 |
39 |
39 |
274 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_inst|mm_interconnect_0|reconfig_cpu_instruction_master_translator_avalon_universal_master_0_agent |
152 |
34 |
59 |
34 |
124 |
34 |
34 |
34 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_inst|mm_interconnect_0|reconfig_cpu_data_master_translator_avalon_universal_master_0_agent |
152 |
34 |
59 |
34 |
124 |
34 |
34 |
34 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_inst|mm_interconnect_0|reconfig_ctrl_ctrl_translator |
98 |
6 |
9 |
6 |
73 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_inst|mm_interconnect_0|reconfig_mem_mem_translator |
98 |
7 |
4 |
7 |
82 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_inst|mm_interconnect_0|reconfig_cpu_instruction_master_translator |
97 |
54 |
0 |
54 |
90 |
54 |
54 |
54 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_inst|mm_interconnect_0|reconfig_cpu_data_master_translator |
99 |
14 |
0 |
14 |
90 |
14 |
14 |
14 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_inst|mm_interconnect_0 |
132 |
0 |
0 |
0 |
153 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_inst|reconfig_cpu|alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_b|the_altsyncram|auto_generated |
44 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_inst|reconfig_cpu|alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_b |
44 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_inst|reconfig_cpu|alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_a|the_altsyncram|auto_generated |
44 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_inst|reconfig_cpu|alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_a |
44 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_inst|reconfig_cpu|the_alt_xcvr_reconfig_cpu_reconfig_cpu_test_bench |
256 |
3 |
222 |
3 |
33 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_inst|reconfig_cpu |
100 |
0 |
31 |
0 |
65 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc|alt_xcvr_reconfig_cpu_inst |
68 |
1 |
0 |
1 |
88 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|soc.sc_soc |
148 |
9 |
0 |
9 |
90 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|direct.sc_direct|mutex_inst |
74 |
0 |
2 |
0 |
71 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|direct.sc_direct |
73 |
0 |
0 |
0 |
71 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|analog.sc_analog|reconfig_analog_sv|inst_xreconf_cif|mutex_inst |
74 |
0 |
2 |
0 |
71 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|analog.sc_analog|reconfig_analog_sv|inst_xreconf_cif|inst_basic_acq |
94 |
0 |
0 |
0 |
104 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|analog.sc_analog|reconfig_analog_sv|inst_xreconf_cif |
95 |
0 |
1 |
0 |
104 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|analog.sc_analog|reconfig_analog_sv|inst_analog_datactrl|inst_p2add_sub_rd|auto_generated |
12 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|analog.sc_analog|reconfig_analog_sv|inst_analog_datactrl|inst_p2add_sub_wr|auto_generated |
12 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|analog.sc_analog|reconfig_analog_sv|inst_analog_datactrl|inst_ptap_add_sub_rd|auto_generated |
12 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|analog.sc_analog|reconfig_analog_sv|inst_analog_datactrl|inst_ptap_add_sub_wr|auto_generated |
12 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|analog.sc_analog|reconfig_analog_sv|inst_analog_datactrl|inst_rmw_sm |
85 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|analog.sc_analog|reconfig_analog_sv|inst_analog_datactrl|inst_analog_ctrlsm |
10 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|analog.sc_analog|reconfig_analog_sv|inst_analog_datactrl |
79 |
6 |
0 |
6 |
83 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|analog.sc_analog|reconfig_analog_sv|inst_xreconf_uif|wait_gen|rst_sync |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|analog.sc_analog|reconfig_analog_sv|inst_xreconf_uif|wait_gen |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|analog.sc_analog|reconfig_analog_sv|inst_xreconf_uif |
106 |
0 |
0 |
0 |
86 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|analog.sc_analog|reconfig_analog_sv |
74 |
0 |
0 |
0 |
72 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|analog.sc_analog |
73 |
0 |
0 |
0 |
72 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|arbiter |
11 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst|inst_reconfig_reset_sync |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig|top_reconfig_inst |
245 |
18 |
0 |
18 |
314 |
18 |
18 |
18 |
0 |
0 |
0 |
0 |
0 |
| inst_reconfig |
227 |
0 |
0 |
0 |
314 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|gen_embedded_reset.reset_controller|g_rx.g_rx[0].g_rx.counter_rx_ready |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|gen_embedded_reset.reset_controller|g_rx.g_rx[0].g_rx.counter_rx_digitalreset |
4 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|gen_embedded_reset.reset_controller|g_rx.g_rx[0].g_rx.counter_rx_analogreset |
4 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|gen_embedded_reset.reset_controller|g_rx.g_rx[0].g_rx.resync_rx_cal_busy |
5 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|gen_embedded_reset.reset_controller|g_tx.g_tx[0].g_tx.counter_tx_ready |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|gen_embedded_reset.reset_controller|g_tx.g_tx[0].g_tx.counter_tx_digitalreset |
4 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|gen_embedded_reset.reset_controller|g_tx.g_tx[0].g_tx.resync_tx_cal_busy |
5 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|gen_embedded_reset.reset_controller|g_pll.counter_pll_powerdown |
4 |
2 |
0 |
2 |
2 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|gen_embedded_reset.reset_controller |
11 |
2 |
0 |
2 |
6 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|csr_pcs|mux_rlv|o_narrow |
6 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|csr_pcs|mux_rlv |
7 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|csr_pcs|mux_tx_phase_comp_fifo_error|o_narrow |
6 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|csr_pcs|mux_tx_phase_comp_fifo_error |
7 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|csr_pcs|mux_rx_bitslipboundaryselectout|o_narrow |
10 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|csr_pcs|mux_rx_bitslipboundaryselectout |
11 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|csr_pcs|mux_rx_phase_comp_fifo_error|o_narrow |
6 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|csr_pcs|mux_rx_phase_comp_fifo_error |
7 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|csr_pcs|mux_rx_a1a2sizeout|o_narrow |
7 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|csr_pcs|mux_rx_a1a2sizeout |
8 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|csr_pcs|mux_rx_disperr|o_narrow |
7 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|csr_pcs|mux_rx_disperr |
8 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|csr_pcs|mux_rx_errdetect|o_narrow |
7 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|csr_pcs|mux_rx_errdetect |
8 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|csr_pcs|mux_rx_syncstatus|o_narrow |
7 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|csr_pcs|mux_rx_syncstatus |
8 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|csr_pcs|mux_rx_patterndetect|o_narrow |
7 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|csr_pcs|mux_rx_patterndetect |
8 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|csr_pcs|wmux_rx_a1a2size|o_narrow |
6 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|csr_pcs|wmux_rx_a1a2size |
7 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|csr_pcs|wmux_rx_bitslip|o_narrow |
6 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|csr_pcs|wmux_rx_bitslip |
7 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|csr_pcs|wmux_rx_bytereversalenable|o_narrow |
6 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|csr_pcs|wmux_rx_bytereversalenable |
7 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|csr_pcs|wmux_rx_bitreversalenable|o_narrow |
6 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|csr_pcs|wmux_rx_bitreversalenable |
7 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|csr_pcs|wmux_rx_enapatternalign|o_narrow |
6 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|csr_pcs|wmux_rx_enapatternalign |
7 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|csr_pcs|wmux_rx_invpolarity|o_narrow |
6 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|csr_pcs|wmux_rx_invpolarity |
7 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|csr_pcs|wmux_tx_bitslipboundaryselect|o_narrow |
10 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|csr_pcs|wmux_tx_bitslipboundaryselect |
15 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|csr_pcs|wmux_tx_invpolarity|o_narrow |
6 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|csr_pcs|wmux_tx_invpolarity |
7 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|csr_pcs |
64 |
0 |
27 |
0 |
43 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|top_wait|rst_sync |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|top_wait |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|csr |
54 |
0 |
29 |
0 |
42 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|transceiver_core|sv_xcvr_data_adapter_inst |
86 |
42 |
32 |
42 |
98 |
42 |
42 |
42 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|transceiver_core|sv_reconfig_bundle_merger_inst |
232 |
0 |
4 |
0 |
232 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_bonded_group.sv_xcvr_native_inst|inst_sv_xcvr_avmm|avmm_interface_insts[0].sv_xcvr_avmm_csr_inst|gen_status_reg_rx.alt_xcvr_resync_inst |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_bonded_group.sv_xcvr_native_inst|inst_sv_xcvr_avmm|avmm_interface_insts[0].sv_xcvr_avmm_csr_inst|gen_status_reg_tx.alt_xcvr_resync_inst |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_bonded_group.sv_xcvr_native_inst|inst_sv_xcvr_avmm|avmm_interface_insts[0].sv_xcvr_avmm_csr_inst |
50 |
23 |
11 |
23 |
35 |
23 |
23 |
23 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_bonded_group.sv_xcvr_native_inst|inst_sv_xcvr_avmm|avmm_interface_insts[0].sv_reconfig_bundle_to_xcvr_inst |
110 |
6 |
22 |
6 |
94 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_bonded_group.sv_xcvr_native_inst|inst_sv_xcvr_avmm |
577 |
74 |
66 |
74 |
100 |
74 |
74 |
74 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_bonded_group.sv_xcvr_native_inst|inst_sv_pcs|ch[0].inst_sv_pcs_ch|inst_sv_hssi_rx_pcs_pma_interface |
139 |
8 |
0 |
8 |
174 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_bonded_group.sv_xcvr_native_inst|inst_sv_pcs|ch[0].inst_sv_pcs_ch|inst_sv_hssi_rx_pld_pcs_interface |
298 |
101 |
0 |
101 |
326 |
101 |
101 |
101 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_bonded_group.sv_xcvr_native_inst|inst_sv_pcs|ch[0].inst_sv_pcs_ch|inst_sv_hssi_common_pld_pcs_interface |
242 |
46 |
0 |
46 |
189 |
46 |
46 |
46 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_bonded_group.sv_xcvr_native_inst|inst_sv_pcs|ch[0].inst_sv_pcs_ch|inst_sv_hssi_8g_tx_pcs |
174 |
1 |
0 |
1 |
194 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_bonded_group.sv_xcvr_native_inst|inst_sv_pcs|ch[0].inst_sv_pcs_ch|inst_sv_hssi_8g_rx_pcs |
313 |
85 |
0 |
85 |
285 |
85 |
85 |
85 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_bonded_group.sv_xcvr_native_inst|inst_sv_pcs|ch[0].inst_sv_pcs_ch|inst_sv_hssi_tx_pld_pcs_interface |
282 |
10 |
0 |
10 |
219 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_bonded_group.sv_xcvr_native_inst|inst_sv_pcs|ch[0].inst_sv_pcs_ch|inst_sv_hssi_tx_pcs_pma_interface |
174 |
114 |
0 |
114 |
105 |
114 |
114 |
114 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_bonded_group.sv_xcvr_native_inst|inst_sv_pcs|ch[0].inst_sv_pcs_ch|inst_sv_hssi_common_pcs_pma_interface |
223 |
46 |
0 |
46 |
192 |
46 |
46 |
46 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_bonded_group.sv_xcvr_native_inst|inst_sv_pcs|ch[0].inst_sv_pcs_ch |
697 |
176 |
22 |
176 |
909 |
176 |
176 |
176 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_bonded_group.sv_xcvr_native_inst|inst_sv_pcs |
633 |
7 |
0 |
7 |
845 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_bonded_group.sv_xcvr_native_inst|inst_sv_pma|tx_pma.sv_tx_pma_inst|tx_pma_insts[0].sv_tx_pma_ch_inst |
163 |
6 |
8 |
6 |
66 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_bonded_group.sv_xcvr_native_inst|inst_sv_pma|tx_pma.sv_tx_pma_inst |
157 |
0 |
0 |
0 |
60 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_bonded_group.sv_xcvr_native_inst|inst_sv_pma|rx_pma.sv_rx_pma_inst |
67 |
0 |
0 |
0 |
160 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_bonded_group.sv_xcvr_native_inst|inst_sv_pma |
162 |
2 |
3 |
2 |
218 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_bonded_group.sv_xcvr_native_inst |
188 |
23 |
0 |
23 |
133 |
23 |
23 |
23 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_tx_plls.gen_tx_plls.tx_plls|pll[0].avmm.sv_xcvr_avmm_csr_inst|gen_status_reg_pll.alt_xcvr_resync_inst |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_tx_plls.gen_tx_plls.tx_plls|pll[0].avmm.sv_xcvr_avmm_csr_inst |
25 |
0 |
14 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_tx_plls.gen_tx_plls.tx_plls|pll[0].avmm.sv_reconfig_bundle_to_xcvr_inst |
110 |
6 |
22 |
6 |
92 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_tx_plls.gen_tx_plls.tx_plls |
73 |
0 |
1 |
0 |
48 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5|transceiver_core |
194 |
4 |
4 |
4 |
147 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst|S5 |
225 |
0 |
5 |
0 |
176 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst2|top_custom_inst |
226 |
21 |
1 |
21 |
161 |
21 |
21 |
21 |
0 |
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0 |
| top_custom_inst2 |
205 |
0 |
0 |
0 |
156 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|gen_embedded_reset.reset_controller|g_rx.g_rx[0].g_rx.counter_rx_ready |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|gen_embedded_reset.reset_controller|g_rx.g_rx[0].g_rx.counter_rx_digitalreset |
4 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|gen_embedded_reset.reset_controller|g_rx.g_rx[0].g_rx.counter_rx_analogreset |
4 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|gen_embedded_reset.reset_controller|g_rx.g_rx[0].g_rx.resync_rx_cal_busy |
5 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|gen_embedded_reset.reset_controller|g_tx.g_tx[0].g_tx.counter_tx_ready |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
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0 |
| top_custom_inst1|top_custom_inst|S5|gen_embedded_reset.reset_controller|g_tx.g_tx[0].g_tx.counter_tx_digitalreset |
4 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|gen_embedded_reset.reset_controller|g_tx.g_tx[0].g_tx.resync_tx_cal_busy |
5 |
0 |
0 |
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3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|gen_embedded_reset.reset_controller|g_pll.counter_pll_powerdown |
4 |
2 |
0 |
2 |
2 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|gen_embedded_reset.reset_controller |
11 |
2 |
0 |
2 |
6 |
2 |
2 |
2 |
0 |
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0 |
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| top_custom_inst1|top_custom_inst|S5|csr_pcs|mux_rlv|o_narrow |
6 |
0 |
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| top_custom_inst1|top_custom_inst|S5|csr_pcs|mux_rlv |
7 |
0 |
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0 |
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0 |
| top_custom_inst1|top_custom_inst|S5|csr_pcs|mux_tx_phase_comp_fifo_error|o_narrow |
6 |
0 |
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| top_custom_inst1|top_custom_inst|S5|csr_pcs|mux_tx_phase_comp_fifo_error |
7 |
0 |
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0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|csr_pcs|mux_rx_bitslipboundaryselectout|o_narrow |
10 |
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5 |
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| top_custom_inst1|top_custom_inst|S5|csr_pcs|mux_rx_bitslipboundaryselectout |
11 |
0 |
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5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|csr_pcs|mux_rx_phase_comp_fifo_error|o_narrow |
6 |
0 |
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0 |
1 |
0 |
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0 |
0 |
0 |
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| top_custom_inst1|top_custom_inst|S5|csr_pcs|mux_rx_phase_comp_fifo_error |
7 |
0 |
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1 |
0 |
0 |
0 |
0 |
0 |
0 |
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0 |
| top_custom_inst1|top_custom_inst|S5|csr_pcs|mux_rx_a1a2sizeout|o_narrow |
7 |
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| top_custom_inst1|top_custom_inst|S5|csr_pcs|mux_rx_a1a2sizeout |
8 |
0 |
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2 |
0 |
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0 |
0 |
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| top_custom_inst1|top_custom_inst|S5|csr_pcs|mux_rx_disperr|o_narrow |
7 |
0 |
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2 |
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| top_custom_inst1|top_custom_inst|S5|csr_pcs|mux_rx_disperr |
8 |
0 |
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2 |
0 |
0 |
0 |
0 |
0 |
0 |
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| top_custom_inst1|top_custom_inst|S5|csr_pcs|mux_rx_errdetect|o_narrow |
7 |
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| top_custom_inst1|top_custom_inst|S5|csr_pcs|mux_rx_errdetect |
8 |
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2 |
0 |
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0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|csr_pcs|mux_rx_syncstatus|o_narrow |
7 |
0 |
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2 |
0 |
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| top_custom_inst1|top_custom_inst|S5|csr_pcs|mux_rx_syncstatus |
8 |
0 |
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2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|csr_pcs|mux_rx_patterndetect|o_narrow |
7 |
0 |
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0 |
2 |
0 |
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0 |
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| top_custom_inst1|top_custom_inst|S5|csr_pcs|mux_rx_patterndetect |
8 |
0 |
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2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|csr_pcs|wmux_rx_a1a2size|o_narrow |
6 |
0 |
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1 |
0 |
0 |
0 |
0 |
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| top_custom_inst1|top_custom_inst|S5|csr_pcs|wmux_rx_a1a2size |
7 |
0 |
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2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
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| top_custom_inst1|top_custom_inst|S5|csr_pcs|wmux_rx_bitslip|o_narrow |
6 |
0 |
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1 |
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| top_custom_inst1|top_custom_inst|S5|csr_pcs|wmux_rx_bitslip |
7 |
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2 |
0 |
0 |
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0 |
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0 |
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| top_custom_inst1|top_custom_inst|S5|csr_pcs|wmux_rx_bytereversalenable|o_narrow |
6 |
0 |
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1 |
0 |
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| top_custom_inst1|top_custom_inst|S5|csr_pcs|wmux_rx_bytereversalenable |
7 |
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2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
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| top_custom_inst1|top_custom_inst|S5|csr_pcs|wmux_rx_bitreversalenable|o_narrow |
6 |
0 |
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1 |
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| top_custom_inst1|top_custom_inst|S5|csr_pcs|wmux_rx_bitreversalenable |
7 |
0 |
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0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|csr_pcs|wmux_rx_enapatternalign|o_narrow |
6 |
0 |
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0 |
0 |
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0 |
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| top_custom_inst1|top_custom_inst|S5|csr_pcs|wmux_rx_enapatternalign |
7 |
0 |
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2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
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| top_custom_inst1|top_custom_inst|S5|csr_pcs|wmux_rx_invpolarity|o_narrow |
6 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|csr_pcs|wmux_rx_invpolarity |
7 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|csr_pcs|wmux_tx_bitslipboundaryselect|o_narrow |
10 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|csr_pcs|wmux_tx_bitslipboundaryselect |
15 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|csr_pcs|wmux_tx_invpolarity|o_narrow |
6 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|csr_pcs|wmux_tx_invpolarity |
7 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|csr_pcs |
64 |
0 |
27 |
0 |
43 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|top_wait|rst_sync |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|top_wait |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|csr |
54 |
0 |
29 |
0 |
42 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|transceiver_core|sv_xcvr_data_adapter_inst |
86 |
42 |
32 |
42 |
98 |
42 |
42 |
42 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|transceiver_core|sv_reconfig_bundle_merger_inst |
232 |
0 |
4 |
0 |
232 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_bonded_group.sv_xcvr_native_inst|inst_sv_xcvr_avmm|avmm_interface_insts[0].sv_xcvr_avmm_csr_inst|gen_status_reg_rx.alt_xcvr_resync_inst |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_bonded_group.sv_xcvr_native_inst|inst_sv_xcvr_avmm|avmm_interface_insts[0].sv_xcvr_avmm_csr_inst|gen_status_reg_tx.alt_xcvr_resync_inst |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_bonded_group.sv_xcvr_native_inst|inst_sv_xcvr_avmm|avmm_interface_insts[0].sv_xcvr_avmm_csr_inst |
50 |
23 |
11 |
23 |
35 |
23 |
23 |
23 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_bonded_group.sv_xcvr_native_inst|inst_sv_xcvr_avmm|avmm_interface_insts[0].sv_reconfig_bundle_to_xcvr_inst |
110 |
6 |
22 |
6 |
94 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_bonded_group.sv_xcvr_native_inst|inst_sv_xcvr_avmm |
577 |
74 |
66 |
74 |
100 |
74 |
74 |
74 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_bonded_group.sv_xcvr_native_inst|inst_sv_pcs|ch[0].inst_sv_pcs_ch|inst_sv_hssi_rx_pcs_pma_interface |
139 |
8 |
0 |
8 |
174 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_bonded_group.sv_xcvr_native_inst|inst_sv_pcs|ch[0].inst_sv_pcs_ch|inst_sv_hssi_rx_pld_pcs_interface |
298 |
101 |
0 |
101 |
326 |
101 |
101 |
101 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_bonded_group.sv_xcvr_native_inst|inst_sv_pcs|ch[0].inst_sv_pcs_ch|inst_sv_hssi_common_pld_pcs_interface |
242 |
46 |
0 |
46 |
189 |
46 |
46 |
46 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_bonded_group.sv_xcvr_native_inst|inst_sv_pcs|ch[0].inst_sv_pcs_ch|inst_sv_hssi_8g_tx_pcs |
174 |
1 |
0 |
1 |
194 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_bonded_group.sv_xcvr_native_inst|inst_sv_pcs|ch[0].inst_sv_pcs_ch|inst_sv_hssi_8g_rx_pcs |
313 |
85 |
0 |
85 |
285 |
85 |
85 |
85 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_bonded_group.sv_xcvr_native_inst|inst_sv_pcs|ch[0].inst_sv_pcs_ch|inst_sv_hssi_tx_pld_pcs_interface |
282 |
10 |
0 |
10 |
219 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_bonded_group.sv_xcvr_native_inst|inst_sv_pcs|ch[0].inst_sv_pcs_ch|inst_sv_hssi_tx_pcs_pma_interface |
174 |
114 |
0 |
114 |
105 |
114 |
114 |
114 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_bonded_group.sv_xcvr_native_inst|inst_sv_pcs|ch[0].inst_sv_pcs_ch|inst_sv_hssi_common_pcs_pma_interface |
223 |
46 |
0 |
46 |
192 |
46 |
46 |
46 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_bonded_group.sv_xcvr_native_inst|inst_sv_pcs|ch[0].inst_sv_pcs_ch |
697 |
176 |
22 |
176 |
909 |
176 |
176 |
176 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_bonded_group.sv_xcvr_native_inst|inst_sv_pcs |
633 |
7 |
0 |
7 |
845 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_bonded_group.sv_xcvr_native_inst|inst_sv_pma|tx_pma.sv_tx_pma_inst|tx_pma_insts[0].sv_tx_pma_ch_inst |
163 |
6 |
8 |
6 |
66 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_bonded_group.sv_xcvr_native_inst|inst_sv_pma|tx_pma.sv_tx_pma_inst |
157 |
0 |
0 |
0 |
60 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_bonded_group.sv_xcvr_native_inst|inst_sv_pma|rx_pma.sv_rx_pma_inst |
67 |
0 |
0 |
0 |
160 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_bonded_group.sv_xcvr_native_inst|inst_sv_pma |
162 |
2 |
3 |
2 |
218 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_bonded_group.sv_xcvr_native_inst |
188 |
23 |
0 |
23 |
133 |
23 |
23 |
23 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_tx_plls.gen_tx_plls.tx_plls|pll[0].avmm.sv_xcvr_avmm_csr_inst|gen_status_reg_pll.alt_xcvr_resync_inst |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_tx_plls.gen_tx_plls.tx_plls|pll[0].avmm.sv_xcvr_avmm_csr_inst |
25 |
0 |
14 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_tx_plls.gen_tx_plls.tx_plls|pll[0].avmm.sv_reconfig_bundle_to_xcvr_inst |
110 |
6 |
22 |
6 |
92 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|transceiver_core|gen.sv_xcvr_native_insts[0].gen_tx_plls.gen_tx_plls.tx_plls |
73 |
0 |
1 |
0 |
48 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5|transceiver_core |
194 |
4 |
4 |
4 |
147 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst|S5 |
225 |
0 |
5 |
0 |
176 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1|top_custom_inst |
226 |
21 |
1 |
21 |
161 |
21 |
21 |
21 |
0 |
0 |
0 |
0 |
0 |
| top_custom_inst1 |
205 |
0 |
0 |
0 |
156 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |