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sys_clk

clock_source v13.0

Parameters clockFrequency 100000000 clockFrequencyKnown true inputClockFrequency 0 resetSynchronousEdges NONE deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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clk_25

clock_source v13.0

Parameters clockFrequency 25000000 clockFrequencyKnown true inputClockFrequency 0 resetSynchronousEdges NONE deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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jtag_master

altera_jtag_avalon_master v13.0

Parameters USE_PLI 0 PLI_PORT 50000 COMPONENT_CLOCK 0 FAST_VER 0 FIFO_DEPTHS 2 AUTO_DEVICE_FAMILY CYCLONEIVE AUTO_DEVICE EP4CE22F17C7 deviceFamily Cyclone IV E generateLegacySim false

  

Software Assignments (none)

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sysid

altera_avalon_sysid_qsys v13.0

Parameters id 2748 timestamp 1376936404 AUTO_CLK_CLOCK_RATE 100000000 AUTO_DEVICE_FAMILY CYCLONEIVE deviceFamily Cyclone IV E generateLegacySim false

  

Software Assignments ID 2748 TIMESTAMP 1376936404

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pio_0

altera_avalon_pio v13.0.1.99.2

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false direction Input edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 32 clockRate 100000000 derived_has_tri false derived_has_out false derived_has_in true derived_do_test_bench_wiring false derived_capture false derived_edge_type NONE derived_irq_type NONE derived_has_irq false deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 CAPTURE 0 DATA_WIDTH 32 DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0 EDGE_TYPE NONE FREQ 100000000 HAS_IN 1 HAS_OUT 0 HAS_TRI 0 IRQ_TYPE NONE RESET_VALUE 0

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rsu_cyclone4_0

rsu_cyclone4 v1.0

Parameters clockFrequency 25000000 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)