| Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
| rst_controller_001|alt_rst_req_sync_uq1 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| rst_controller_001|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| rst_controller_001 |
33 |
31 |
0 |
31 |
1 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
| rst_controller|alt_rst_req_sync_uq1 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| rst_controller|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| rst_controller |
33 |
31 |
0 |
31 |
1 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|emif_0_example_design_ctrl_amm_0_translator |
736 |
4 |
6 |
4 |
716 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0|tg_ctrl_amm_0_translator |
733 |
15 |
2 |
15 |
730 |
15 |
15 |
15 |
0 |
0 |
0 |
0 |
0 |
| mm_interconnect_0 |
727 |
0 |
2 |
0 |
716 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|read_compare_inst|be_gen.be_gen_inst|lfsr_gen[1].lfsr_inst |
3 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|read_compare_inst|be_gen.be_gen_inst|lfsr_gen[0].lfsr_inst |
3 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|read_compare_inst|be_gen.be_gen_inst |
3 |
0 |
0 |
0 |
40 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|read_compare_inst|data_gen_inst|lfsr_gen[15].lfsr_inst |
3 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|read_compare_inst|data_gen_inst|lfsr_gen[14].lfsr_inst |
3 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|read_compare_inst|data_gen_inst|lfsr_gen[13].lfsr_inst |
3 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|read_compare_inst|data_gen_inst|lfsr_gen[12].lfsr_inst |
3 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|read_compare_inst|data_gen_inst|lfsr_gen[11].lfsr_inst |
3 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|read_compare_inst|data_gen_inst|lfsr_gen[10].lfsr_inst |
3 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|read_compare_inst|data_gen_inst|lfsr_gen[9].lfsr_inst |
3 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|read_compare_inst|data_gen_inst|lfsr_gen[8].lfsr_inst |
3 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|read_compare_inst|data_gen_inst|lfsr_gen[7].lfsr_inst |
3 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|read_compare_inst|data_gen_inst|lfsr_gen[6].lfsr_inst |
3 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|read_compare_inst|data_gen_inst|lfsr_gen[5].lfsr_inst |
3 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|read_compare_inst|data_gen_inst|lfsr_gen[4].lfsr_inst |
3 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|read_compare_inst|data_gen_inst|lfsr_gen[3].lfsr_inst |
3 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|read_compare_inst|data_gen_inst|lfsr_gen[2].lfsr_inst |
3 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|read_compare_inst|data_gen_inst|lfsr_gen[1].lfsr_inst |
3 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|read_compare_inst|data_gen_inst|lfsr_gen[0].lfsr_inst |
3 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|read_compare_inst|data_gen_inst |
3 |
0 |
0 |
0 |
320 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|read_compare_inst |
325 |
1 |
0 |
1 |
322 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|not_srw.avl_tg_avl_mm_if_inst|avalon_traffic_fifo|scfifo_inst|subfifo|fifo_state|is_almost_full_compare|auto_generated |
6 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|not_srw.avl_tg_avl_mm_if_inst|avalon_traffic_fifo|scfifo_inst|subfifo|fifo_state|is_almost_empty_compare|auto_generated |
6 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|not_srw.avl_tg_avl_mm_if_inst|avalon_traffic_fifo|scfifo_inst|subfifo|rd_ptr|auto_generated |
5 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|not_srw.avl_tg_avl_mm_if_inst|avalon_traffic_fifo|scfifo_inst|subfifo|last_row_data_out_mux|auto_generated |
331 |
0 |
0 |
0 |
41 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|not_srw.avl_tg_avl_mm_if_inst|avalon_traffic_fifo |
45 |
0 |
0 |
0 |
43 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|not_srw.avl_tg_avl_mm_if_inst |
483 |
0 |
0 |
0 |
404 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|not_srw.amm_1x_bridge |
403 |
0 |
0 |
0 |
401 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|driver_fsm_inst|template_stage_inst |
6 |
32 |
0 |
32 |
35 |
32 |
32 |
32 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|driver_fsm_inst|byteenable_stage_inst |
7 |
32 |
1 |
32 |
36 |
32 |
32 |
32 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|driver_fsm_inst|block_rw_stage_inst |
6 |
0 |
0 |
0 |
35 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|driver_fsm_inst|single_rw_stage_inst |
6 |
0 |
0 |
0 |
35 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|driver_fsm_inst |
8 |
34 |
0 |
34 |
70 |
34 |
34 |
34 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|addr_burstcount_fifo|scfifo_inst|subfifo|fifo_state|is_almost_full_compare|auto_generated |
6 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|addr_burstcount_fifo|scfifo_inst|subfifo|fifo_state|is_almost_empty_compare|auto_generated |
6 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|addr_burstcount_fifo|scfifo_inst|subfifo|rd_ptr|auto_generated |
5 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|addr_burstcount_fifo|scfifo_inst|subfifo|last_row_data_out_mux|auto_generated |
307 |
0 |
0 |
0 |
38 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|addr_burstcount_fifo |
42 |
0 |
0 |
0 |
39 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|be_gen.inv_be_gen_inst|lfsr_gen[1].lfsr_inst |
3 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|be_gen.inv_be_gen_inst|lfsr_gen[0].lfsr_inst |
3 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|be_gen.inv_be_gen_inst |
3 |
0 |
0 |
0 |
40 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|be_gen.be_gen_inst|lfsr_gen[1].lfsr_inst |
3 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|be_gen.be_gen_inst|lfsr_gen[0].lfsr_inst |
3 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|be_gen.be_gen_inst |
3 |
0 |
0 |
0 |
40 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|data_gen_inst|lfsr_gen[15].lfsr_inst |
3 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|data_gen_inst|lfsr_gen[14].lfsr_inst |
3 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|data_gen_inst|lfsr_gen[13].lfsr_inst |
3 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|data_gen_inst|lfsr_gen[12].lfsr_inst |
3 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|data_gen_inst|lfsr_gen[11].lfsr_inst |
3 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|data_gen_inst|lfsr_gen[10].lfsr_inst |
3 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|data_gen_inst|lfsr_gen[9].lfsr_inst |
3 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|data_gen_inst|lfsr_gen[8].lfsr_inst |
3 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|data_gen_inst|lfsr_gen[7].lfsr_inst |
3 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|data_gen_inst|lfsr_gen[6].lfsr_inst |
3 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|data_gen_inst|lfsr_gen[5].lfsr_inst |
3 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|data_gen_inst|lfsr_gen[4].lfsr_inst |
3 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|data_gen_inst|lfsr_gen[3].lfsr_inst |
3 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|data_gen_inst|lfsr_gen[2].lfsr_inst |
3 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|data_gen_inst|lfsr_gen[1].lfsr_inst |
3 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|data_gen_inst|lfsr_gen[0].lfsr_inst |
3 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|data_gen_inst |
3 |
0 |
0 |
0 |
320 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|addr_gen_inst|template_addr_gen_inst |
3 |
32 |
0 |
32 |
33 |
32 |
32 |
32 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|addr_gen_inst|rand_seq_addr_gen_inst|burst_boundary_addr_gen_inst |
32 |
0 |
7 |
0 |
25 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|addr_gen_inst|rand_seq_addr_gen_inst|rand_seq_prob|random_gen.lfsr_inst |
3 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|addr_gen_inst|rand_seq_addr_gen_inst|rand_seq_prob |
3 |
0 |
0 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|addr_gen_inst|rand_seq_addr_gen_inst|rand_burstcount|power_of_two_false.rand_burstcount|random_gen.lfsr_inst |
3 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|addr_gen_inst|rand_seq_addr_gen_inst|rand_burstcount|power_of_two_false.rand_burstcount |
3 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|addr_gen_inst|rand_seq_addr_gen_inst|rand_burstcount |
3 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|addr_gen_inst|rand_seq_addr_gen_inst|rand_addr_high |
3 |
0 |
0 |
0 |
11 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|addr_gen_inst|rand_seq_addr_gen_inst|rand_addr_low |
3 |
0 |
0 |
0 |
13 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|addr_gen_inst|rand_seq_addr_gen_inst |
3 |
0 |
0 |
0 |
33 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|addr_gen_inst|rand_addr_gen_inst|burst_boundary_addr_gen_inst |
32 |
1 |
7 |
1 |
25 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|addr_gen_inst|rand_addr_gen_inst|rand_burstcount|power_of_two_false.rand_burstcount|random_gen.lfsr_inst |
3 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|addr_gen_inst|rand_addr_gen_inst|rand_burstcount|power_of_two_false.rand_burstcount |
3 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|addr_gen_inst|rand_addr_gen_inst|rand_burstcount |
3 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|addr_gen_inst|rand_addr_gen_inst|rand_addr_high |
3 |
0 |
0 |
0 |
11 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|addr_gen_inst|rand_addr_gen_inst|rand_addr_low |
3 |
0 |
0 |
0 |
13 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|addr_gen_inst|rand_addr_gen_inst |
3 |
0 |
0 |
0 |
33 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|addr_gen_inst|seq_addr_gen_inst|burst_boundary_addr_gen_inst |
32 |
0 |
7 |
0 |
25 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|addr_gen_inst|seq_addr_gen_inst|rand_burstcount|power_of_two_false.rand_burstcount|random_gen.lfsr_inst |
3 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|addr_gen_inst|seq_addr_gen_inst|rand_burstcount|power_of_two_false.rand_burstcount |
3 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|addr_gen_inst|seq_addr_gen_inst|rand_burstcount |
3 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|addr_gen_inst|seq_addr_gen_inst |
3 |
0 |
0 |
0 |
33 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|addr_gen_inst |
35 |
6 |
0 |
6 |
39 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst|reset_sync_inst |
2 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| tg|not_srw.gen_avl_mm_driver[0].normal.inst |
325 |
1 |
0 |
1 |
723 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| tg |
2662 |
2338 |
0 |
2338 |
403 |
2338 |
2338 |
2338 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|rst_controller|alt_rst_req_sync_uq1 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|rst_controller|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|rst_controller |
33 |
31 |
0 |
31 |
1 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|mm_interconnect_0|arch_cal_debug_translator |
115 |
4 |
8 |
4 |
96 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|mm_interconnect_0|col_if_to_ioaux_translator |
114 |
12 |
2 |
12 |
109 |
12 |
12 |
12 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|mm_interconnect_0 |
106 |
0 |
0 |
0 |
96 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|col_if|mm_interconnect_0|avl_bridge_out_s0_translator |
115 |
4 |
2 |
4 |
104 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|col_if|mm_interconnect_0|colmaster_master_translator |
116 |
13 |
2 |
13 |
109 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|col_if|mm_interconnect_0 |
107 |
0 |
1 |
0 |
104 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|col_if|colmaster|rst_controller|alt_rst_req_sync_uq1 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|col_if|colmaster|rst_controller|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|col_if|colmaster|rst_controller |
33 |
31 |
0 |
31 |
1 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|col_if|colmaster|p2b_adapter |
14 |
8 |
2 |
8 |
20 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|col_if|colmaster|b2p_adapter |
22 |
0 |
2 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|col_if|colmaster|transacto|p2m |
48 |
0 |
0 |
0 |
82 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|col_if|colmaster|transacto |
48 |
0 |
0 |
0 |
82 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|col_if|colmaster|p2b |
22 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|col_if|colmaster|b2p |
12 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|col_if|colmaster|fifo |
53 |
41 |
0 |
41 |
10 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|col_if|colmaster|timing_adt |
12 |
0 |
3 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|col_if|colmaster|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|source_crosser|crosser |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|col_if|colmaster|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|source_crosser |
13 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|col_if|colmaster|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|sink_crosser|output_stage |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|col_if|colmaster|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|sink_crosser |
14 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|col_if|colmaster|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|jtag_streaming|idle_inserter |
12 |
1 |
0 |
1 |
10 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|col_if|colmaster|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|jtag_streaming|idle_remover |
12 |
2 |
0 |
2 |
10 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|col_if|colmaster|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|jtag_streaming |
20 |
1 |
0 |
1 |
16 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|col_if|colmaster|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming |
19 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|col_if|colmaster|jtag_phy_embedded_in_jtag_master|node |
4 |
3 |
0 |
3 |
8 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|col_if|colmaster|jtag_phy_embedded_in_jtag_master |
38 |
27 |
0 |
27 |
11 |
27 |
27 |
27 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|col_if|colmaster |
36 |
0 |
0 |
0 |
70 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|col_if|avl_bridge_out |
108 |
2 |
0 |
2 |
104 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|col_if |
36 |
0 |
0 |
0 |
70 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|hmc.amm.data_if_inst |
1488 |
1112 |
808 |
1112 |
1792 |
1112 |
1112 |
1112 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|hmc_mmr_if_inst |
162 |
8 |
0 |
8 |
170 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|hmc_sideband_if_inst |
207 |
27 |
80 |
27 |
180 |
27 |
27 |
27 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|hmc_avl_if_inst |
214 |
60 |
138 |
60 |
136 |
60 |
60 |
60 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|seq_if_inst|gen_oct_cal_req.gen_oct_cal_req_no_hps.oct_cal_req_regs |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|seq_if_inst|afi_cal_fail_regs |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|seq_if_inst|afi_cal_success_regs |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|seq_if_inst|afi_seq_busy_regs |
6 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|seq_if_inst|afi_wlat_regs |
8 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|seq_if_inst|afi_rlat_regs |
8 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|seq_if_inst|gen_oct_cal_rdy.gen_oct_cal_rdy_no_hps.oct_cal_rdy_regs |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|seq_if_inst|afi_ctl_long_idle_regs |
6 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|seq_if_inst|afi_ctl_refresh_done_regs |
6 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|seq_if_inst|afi_cal_req_regs |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|seq_if_inst |
37 |
8 |
12 |
8 |
37 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|io_tiles_inst |
1999 |
416 |
169 |
416 |
1493 |
416 |
416 |
416 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|io_aux_inst |
184 |
3 |
9 |
3 |
218 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[4].ub1 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[4].gen_x8.ub0 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[4].b |
38 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[3].ub1 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[3].gen_x8.ub0 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[3].b |
38 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[2].ub1 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[2].gen_x8.ub0 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[2].b |
38 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[1].ub1 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[1].gen_x8.ub0 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[1].b |
38 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[0].ub1 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[0].gen_x8.ub0 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[0].b |
38 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dq.inst[39].b |
35 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dq.inst[38].b |
35 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dq.inst[37].b |
35 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dq.inst[36].b |
35 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dq.inst[35].b |
35 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dq.inst[34].b |
35 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dq.inst[33].b |
35 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dq.inst[32].b |
35 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dq.inst[31].b |
35 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dq.inst[30].b |
35 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dq.inst[29].b |
35 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dq.inst[28].b |
35 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dq.inst[27].b |
35 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dq.inst[26].b |
35 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dq.inst[25].b |
35 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dq.inst[24].b |
35 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dq.inst[23].b |
35 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dq.inst[22].b |
35 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dq.inst[21].b |
35 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dq.inst[20].b |
35 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dq.inst[19].b |
35 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dq.inst[18].b |
35 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dq.inst[17].b |
35 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dq.inst[16].b |
35 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dq.inst[15].b |
35 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dq.inst[14].b |
35 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dq.inst[13].b |
35 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dq.inst[12].b |
35 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dq.inst[11].b |
35 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dq.inst[10].b |
35 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dq.inst[9].b |
35 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dq.inst[8].b |
35 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dq.inst[7].b |
35 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dq.inst[6].b |
35 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dq.inst[5].b |
35 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dq.inst[4].b |
35 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dq.inst[3].b |
35 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dq.inst[2].b |
35 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dq.inst[1].b |
35 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dq.inst[0].b |
35 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dm.inst[4].ubuf |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dm.inst[4].b |
33 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dm.inst[3].ubuf |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dm.inst[3].b |
33 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dm.inst[2].ubuf |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dm.inst[2].b |
33 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dm.inst[1].ubuf |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dm.inst[1].b |
33 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dm.inst[0].ubuf |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_dm.inst[0].b |
33 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_reset_n.inst[0].ubuf |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_reset_n.inst[0].b |
33 |
0 |
32 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_we_n.inst[0].ubuf |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_we_n.inst[0].b |
33 |
0 |
32 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_cas_n.inst[0].ubuf |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_cas_n.inst[0].b |
33 |
0 |
32 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_ras_n.inst[0].ubuf |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_ras_n.inst[0].b |
33 |
0 |
32 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_odt.inst[0].ubuf |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_odt.inst[0].b |
33 |
0 |
32 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_cs_n.inst[0].ubuf |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_cs_n.inst[0].b |
33 |
0 |
32 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_cke.inst[0].ubuf |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_cke.inst[0].b |
33 |
0 |
32 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_ba.inst[2].ubuf |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_ba.inst[2].b |
33 |
0 |
32 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_ba.inst[1].ubuf |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_ba.inst[1].b |
33 |
0 |
32 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_ba.inst[0].ubuf |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_ba.inst[0].b |
33 |
0 |
32 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_a.inst[14].ubuf |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_a.inst[14].b |
33 |
0 |
32 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_a.inst[13].ubuf |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_a.inst[13].b |
33 |
0 |
32 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_a.inst[12].ubuf |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_a.inst[12].b |
33 |
0 |
32 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_a.inst[11].ubuf |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_a.inst[11].b |
33 |
0 |
32 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_a.inst[10].ubuf |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_a.inst[10].b |
33 |
0 |
32 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_a.inst[9].ubuf |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_a.inst[9].b |
33 |
0 |
32 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_a.inst[8].ubuf |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_a.inst[8].b |
33 |
0 |
32 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_a.inst[7].ubuf |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_a.inst[7].b |
33 |
0 |
32 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_a.inst[6].ubuf |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_a.inst[6].b |
33 |
0 |
32 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_a.inst[5].ubuf |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_a.inst[5].b |
33 |
0 |
32 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_a.inst[4].ubuf |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_a.inst[4].b |
33 |
0 |
32 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_a.inst[3].ubuf |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_a.inst[3].b |
33 |
0 |
32 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_a.inst[2].ubuf |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_a.inst[2].b |
33 |
0 |
32 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_a.inst[1].ubuf |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_a.inst[1].b |
33 |
0 |
32 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_a.inst[0].ubuf |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_a.inst[0].b |
33 |
0 |
32 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_ck.inst[0].ub1 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_ck.inst[0].ub0 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|gen_mem_ck.inst[0].b |
34 |
0 |
32 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|unused_dqs_bus[2].ub1 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|unused_dqs_bus[2].ub0 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|unused_dqs_bus[1].ub1 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|unused_dqs_bus[1].ub0 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|unused_dqs_bus[0].ub1 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|unused_dqs_bus[0].ub0 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|unused_pin[13].ub |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|unused_pin[12].ub |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|unused_pin[11].ub |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|unused_pin[10].ub |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|unused_pin[9].ub |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|unused_pin[8].ub |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|unused_pin[7].ub |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|unused_pin[6].ub |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|unused_pin[5].ub |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|unused_pin[4].ub |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|unused_pin[3].ub |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|unused_pin[2].ub |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|unused_pin[1].ub |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst|unused_pin[0].ub |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|bufs_inst |
331 |
29 |
117 |
29 |
173 |
29 |
29 |
29 |
55 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|non_hps.core_clks_rsts_inst |
40 |
28 |
34 |
28 |
47 |
28 |
28 |
28 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|oct_inst|cal_oct.manual_oct_cal.oct_inst|altera_oct_um_fsm_i |
3 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|oct_inst|cal_oct.manual_oct_cal.oct_inst |
5 |
353 |
0 |
353 |
386 |
353 |
353 |
353 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|oct_inst |
8 |
0 |
3 |
0 |
33 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|pll_extra_clks_inst |
10 |
1 |
6 |
1 |
5 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst|pll_inst |
12 |
0 |
0 |
0 |
23 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch|arch_inst |
5434 |
4104 |
4135 |
4104 |
5195 |
4104 |
4104 |
4104 |
55 |
0 |
0 |
0 |
0 |
| emif_0_example_design|arch |
5434 |
4973 |
0 |
4973 |
392 |
4973 |
4973 |
4973 |
50 |
0 |
0 |
0 |
0 |
| emif_0_example_design |
397 |
0 |
0 |
0 |
358 |
0 |
0 |
0 |
50 |
0 |
0 |
0 |
0 |
| ed_iss_0 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |