diff -rupN a/uboot-socfpga/drivers/spi/cadence_qspi_apb.c b/uboot-socfpga/drivers/spi/cadence_qspi_apb.c
--- a/uboot-socfpga/drivers/spi/cadence_qspi_apb.c	2014-10-20 10:24:49.954451835 -0500
+++ b/uboot-socfpga/drivers/spi/cadence_qspi_apb.c	2014-10-20 10:25:19.219451246 -0500
@@ -73,6 +73,7 @@
 #define	CQSPI_REG_CONFIG_IDLE_LSB		31
 #define	CQSPI_REG_CONFIG_CHIPSELECT_MASK	0xF
 #define	CQSPI_REG_CONFIG_BAUD_MASK		0xF
+#define CQSPI_REG_CCONFIG_ENAHBREMAP_MASK       (1 << 16)
 
 #define	CQSPI_REG_RD_INSTR			0x04
 #define	CQSPI_REG_RD_INSTR_OPCODE_LSB		0
@@ -884,11 +885,19 @@ void cadence_qspi_apb_enter_xip(void *re
 {
 	unsigned int reg;
 
+#if CONFIG_SPL_SPI_XIP_REMAPADDR    
+	/* set the remap address */
+	CQSPI_WRITEL(CONFIG_SPL_SPI_XIP_REMAPADDR, reg_base + CQSPI_REG_REMAP);    
+#endif    
+
 	/* enter XiP mode immediately and enable direct mode */
 	reg = CQSPI_READL(reg_base + CQSPI_REG_CONFIG);
 	reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
 	reg |= CQSPI_REG_CONFIG_DIRECT_MASK;
 	reg |= CQSPI_REG_CONFIG_XIP_IMM_MASK;
+#if CONFIG_SPL_SPI_XIP_REMAPADDR        
+    reg |= CQSPI_REG_CCONFIG_ENAHBREMAP_MASK;
+#endif    
 	CQSPI_WRITEL(reg, reg_base + CQSPI_REG_CONFIG);
 
 	/* keep the XiP mode */
diff -rupN a/uboot-socfpga/include/configs/socfpga_common.h b/uboot-socfpga/include/configs/socfpga_common.h
--- a/uboot-socfpga/include/configs/socfpga_common.h	2014-10-20 10:24:49.826447495 -0500
+++ b/uboot-socfpga/include/configs/socfpga_common.h	2014-10-20 10:25:36.834040858 -0500
@@ -662,9 +662,11 @@
 /* Support for drivers/spi/libspi.o in SPL binary */
 #define CONFIG_SPL_SPI_SUPPORT
 /* Support for XiP */
-#undef CONFIG_SPL_SPI_XIP
+#define CONFIG_SPL_SPI_XIP
 /* the XiP address that SPL will jump to */
 #define CONFIG_SPL_SPI_XIP_ADDR		0xFFA00040
+/* Offset added to the incoming AHB address to determine the address used by the FLASH device */
+#define CONFIG_SPL_SPI_XIP_REMAPADDR    0x00100000
 /* SPL SPI flash Chip select */
 #define CONFIG_SPL_SPI_CS		0
 /* SPL SPI flash Bus Number */