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Board Update Portal
MAX 10 FPGA Development Kit

This Board Update Portal (BUP) web page is being served by the BUP design running in the FPGA on your development board, it allows you to write your software image into User Software block of the flash and provides links to useful information on the Altera® website. The BUP design contains a Nios® II processor and the Triple Speed Ethernet media access control (MAC) MegaCore® function. When you install the development kit design files on your system, the design files for the Board Update Portal FPGA design are installed in the
…kits/max10_10m50daf484c6ges_fpga/examples/board_update_portal
directory. This design is one example of how to remotely update an FPGA system over Ethernet. Remote update can be accomplished without a web server, and it can also be used to update just the firmware of an embedded FPGA system. Please see application note AN429: Remote Configuration Over Ethernet with the Nios II Processor (PDF) to learn more about remote update.

Instructions on preparing your own .elf files for uploading to flash via the Board Update Portal are available here.

Upload New Designs to User Portion of Flash Memory
Flash Factory File:
Software File Name:
 
 
MAX 10 FPGA Development Kit
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