hdmi_qsys

2015.03.25.15:06:12 Datasheet
Overview
  clk_50  hdmi_qsys

All Components
   alt_vip_cl_swi_0 alt_vip_cl_swi 15.0
   altpll_0 altpll 15.0
   hdmi_tx_int_n altera_avalon_pio 15.0
   opencores_i2c_0 opencores_i2c 9.1
   product_info_0 product_info 1.0
Memory Map
master_0
 master
  alt_vip_cl_swi_0
control  0x00000080
  altpll_0
pll_slave  0x00000010
  hdmi_tx_int_n
s1  0x00000040
  opencores_i2c_0
avalon_slave_0  0x00000020
  product_info_0
avalon_slave_0  0x00000000

alt_vip_cl_cvo_0

alt_vip_cl_cvo v15.0
alt_vip_cl_swi_0 dout0   alt_vip_cl_cvo_0
  din
altpll_0 c0  
  main_clock
clk_50 clk_reset  
  main_reset


Parameters

NUMBER_OF_COLOUR_PLANES 3
COLOUR_PLANES_ARE_IN_PARALLEL 1
BPS 8
INTERLACED 0
H_ACTIVE_PIXELS 1920
V_ACTIVE_LINES 1080
ACCEPT_COLOURS_IN_SEQ 0
FIFO_DEPTH 1920
CLOCKS_ARE_SAME 1
USE_CONTROL 0
NO_OF_MODES 1
THRESHOLD 1919
STD_WIDTH 1
GENERATE_SYNC 0
USE_EMBEDDED_SYNCS 0
AP_LINE 0
V_BLANK 0
H_BLANK 0
H_SYNC_LENGTH 44
H_FRONT_PORCH 88
H_BACK_PORCH 148
V_SYNC_LENGTH 5
V_FRONT_PORCH 4
V_BACK_PORCH 36
F_RISING_EDGE 0
F_FALLING_EDGE 0
FIELD0_V_RISING_EDGE 0
FIELD0_V_BLANK 0
FIELD0_V_SYNC_LENGTH 0
FIELD0_V_FRONT_PORCH 0
FIELD0_V_BACK_PORCH 0
ANC_LINE 0
FIELD0_ANC_LINE 0
PIXELS_IN_PARALLEL 1
NO_OF_CHANNELS 1
SRC_WIDTH 8
DST_WIDTH 8
CONTEXT_WIDTH 8
TASK_WIDTH 8
AUTO_DEVICE_FAMILY MAX10FPGA
AUTO_DEVICE 10M50DAF484C6GES
AUTO_DEVICE_SPEEDGRADE 6
deviceFamily MAX 10
generateLegacySim false
  

Software Assignments

(none)

alt_vip_cl_swi_0

alt_vip_cl_swi v15.0
master_0 master   alt_vip_cl_swi_0
  control
tpg_CB_1080 dout  
  din0
tpg_Red_1080 dout  
  din1
tpg_Green_1080 dout  
  din2
tpg_Blue_1080 dout  
  din3
tpg_White_1080 dout  
  din4
tpg_Black_1080 dout  
  din5
altpll_0 c0  
  main_clock
clk_50 clk_reset  
  main_clock_reset
dout0   alt_vip_cl_cvo_0
  din


Parameters

READY_LATENCY 1
NO_OF_INPUTS 6
NO_OF_OUTPUTS 1
BPS 8
NUMBER_OF_COLOR_PLANES 3
PIXELS_IN_PARALLEL 1
COLOR_PLANES_ARE_IN_PARALLEL true
CHANNEL_WIDTH 0
NUM_CHANNELS 0
ALPHA_ENABLED false
AUTO_DEVICE_FAMILY MAX10FPGA
AUTO_MAIN_CLOCK_CLOCK_RATE 150000000
deviceFamily MAX 10
generateLegacySim false
  

Software Assignments

(none)

altpll_0

altpll v15.0
master_0 master   altpll_0
  pll_slave
clk_50 clk  
  inclk_interface
clk_reset  
  inclk_interface_reset
c0   disp_refclk
  in_clk
c0   tpg_CB_1080
  main_clock
c0   alt_vip_cl_cvo_0
  main_clock
c0   tpg_Red_1080
  main_clock
c0   tpg_Blue_1080
  main_clock
c0   tpg_White_1080
  main_clock
c0   tpg_Black_1080
  main_clock
c0   alt_vip_cl_swi_0
  main_clock
c0   tpg_Green_1080
  main_clock


Parameters

HIDDEN_CUSTOM_ELABORATION altpll_avalon_elaboration
HIDDEN_CUSTOM_POST_EDIT altpll_avalon_post_edit
INTENDED_DEVICE_FAMILY MAX 10
WIDTH_CLOCK 5
WIDTH_PHASECOUNTERSELECT
PRIMARY_CLOCK
INCLK0_INPUT_FREQUENCY 20000
INCLK1_INPUT_FREQUENCY
OPERATION_MODE NORMAL
PLL_TYPE AUTO
QUALIFY_CONF_DONE
COMPENSATE_CLOCK CLK0
SCAN_CHAIN
GATE_LOCK_SIGNAL
GATE_LOCK_COUNTER
LOCK_HIGH
LOCK_LOW
VALID_LOCK_MULTIPLIER
INVALID_LOCK_MULTIPLIER
SWITCH_OVER_ON_LOSSCLK
SWITCH_OVER_ON_GATED_LOCK
ENABLE_SWITCH_OVER_COUNTER
SKIP_VCO
SWITCH_OVER_COUNTER
SWITCH_OVER_TYPE
FEEDBACK_SOURCE
BANDWIDTH
BANDWIDTH_TYPE AUTO
SPREAD_FREQUENCY
DOWN_SPREAD
SELF_RESET_ON_GATED_LOSS_LOCK
SELF_RESET_ON_LOSS_LOCK
CLK0_MULTIPLY_BY 3
CLK1_MULTIPLY_BY
CLK2_MULTIPLY_BY
CLK3_MULTIPLY_BY
CLK4_MULTIPLY_BY
CLK5_MULTIPLY_BY
CLK6_MULTIPLY_BY
CLK7_MULTIPLY_BY
CLK8_MULTIPLY_BY
CLK9_MULTIPLY_BY
EXTCLK0_MULTIPLY_BY
EXTCLK1_MULTIPLY_BY
EXTCLK2_MULTIPLY_BY
EXTCLK3_MULTIPLY_BY
CLK0_DIVIDE_BY 1
CLK1_DIVIDE_BY
CLK2_DIVIDE_BY
CLK3_DIVIDE_BY
CLK4_DIVIDE_BY
CLK5_DIVIDE_BY
CLK6_DIVIDE_BY
CLK7_DIVIDE_BY
CLK8_DIVIDE_BY
CLK9_DIVIDE_BY
EXTCLK0_DIVIDE_BY
EXTCLK1_DIVIDE_BY
EXTCLK2_DIVIDE_BY
EXTCLK3_DIVIDE_BY
CLK0_PHASE_SHIFT 0
CLK1_PHASE_SHIFT
CLK2_PHASE_SHIFT
CLK3_PHASE_SHIFT
CLK4_PHASE_SHIFT
CLK5_PHASE_SHIFT
CLK6_PHASE_SHIFT
CLK7_PHASE_SHIFT
CLK8_PHASE_SHIFT
CLK9_PHASE_SHIFT
EXTCLK0_PHASE_SHIFT
EXTCLK1_PHASE_SHIFT
EXTCLK2_PHASE_SHIFT
EXTCLK3_PHASE_SHIFT
CLK0_DUTY_CYCLE 50
CLK1_DUTY_CYCLE
CLK2_DUTY_CYCLE
CLK3_DUTY_CYCLE
CLK4_DUTY_CYCLE
CLK5_DUTY_CYCLE
CLK6_DUTY_CYCLE
CLK7_DUTY_CYCLE
CLK8_DUTY_CYCLE
CLK9_DUTY_CYCLE
EXTCLK0_DUTY_CYCLE
EXTCLK1_DUTY_CYCLE
EXTCLK2_DUTY_CYCLE
EXTCLK3_DUTY_CYCLE
PORT_clkena0 PORT_UNUSED
PORT_clkena1 PORT_UNUSED
PORT_clkena2 PORT_UNUSED
PORT_clkena3 PORT_UNUSED
PORT_clkena4 PORT_UNUSED
PORT_clkena5 PORT_UNUSED
PORT_extclkena0
PORT_extclkena1
PORT_extclkena2
PORT_extclkena3
PORT_extclk0 PORT_UNUSED
PORT_extclk1 PORT_UNUSED
PORT_extclk2 PORT_UNUSED
PORT_extclk3 PORT_UNUSED
PORT_CLKBAD0 PORT_UNUSED
PORT_CLKBAD1 PORT_UNUSED
PORT_clk0 PORT_USED
PORT_clk1 PORT_UNUSED
PORT_clk2 PORT_UNUSED
PORT_clk3 PORT_UNUSED
PORT_clk4 PORT_UNUSED
PORT_clk5 PORT_UNUSED
PORT_clk6
PORT_clk7
PORT_clk8
PORT_clk9
PORT_SCANDATA PORT_UNUSED
PORT_SCANDATAOUT PORT_UNUSED
PORT_SCANDONE PORT_UNUSED
PORT_SCLKOUT1
PORT_SCLKOUT0
PORT_ACTIVECLOCK PORT_UNUSED
PORT_CLKLOSS PORT_UNUSED
PORT_INCLK1 PORT_UNUSED
PORT_INCLK0 PORT_USED
PORT_FBIN PORT_UNUSED
PORT_PLLENA PORT_UNUSED
PORT_CLKSWITCH PORT_UNUSED
PORT_ARESET PORT_USED
PORT_PFDENA PORT_UNUSED
PORT_SCANCLK PORT_UNUSED
PORT_SCANACLR PORT_UNUSED
PORT_SCANREAD PORT_UNUSED
PORT_SCANWRITE PORT_UNUSED
PORT_ENABLE0
PORT_ENABLE1
PORT_LOCKED PORT_USED
PORT_CONFIGUPDATE PORT_UNUSED
PORT_FBOUT
PORT_PHASEDONE PORT_UNUSED
PORT_PHASESTEP PORT_UNUSED
PORT_PHASEUPDOWN PORT_UNUSED
PORT_SCANCLKENA PORT_UNUSED
PORT_PHASECOUNTERSELECT PORT_UNUSED
PORT_VCOOVERRANGE
PORT_VCOUNDERRANGE
DPA_MULTIPLY_BY
DPA_DIVIDE_BY
DPA_DIVIDER
VCO_MULTIPLY_BY
VCO_DIVIDE_BY
SCLKOUT0_PHASE_SHIFT
SCLKOUT1_PHASE_SHIFT
VCO_FREQUENCY_CONTROL
VCO_PHASE_SHIFT_STEP
USING_FBMIMICBIDIR_PORT
SCAN_CHAIN_MIF_FILE
AVALON_USE_SEPARATE_SYSCLK NO
HIDDEN_CONSTANTS CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_UNUSED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 3 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#PORT_ARESET PORT_USED CT#BANDWIDTH_TYPE AUTO CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#PORT_LOCKED PORT_USED
HIDDEN_PRIVATES PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 1 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 0 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ0 100.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE 6 PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE0 150.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK0 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#CLKLOSS_CHECK 0 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR0 3 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE0 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1422251063372973.mif PT#ACTIVECLK_CHECK 0
HIDDEN_USED_PORTS UP#locked used UP#c0 used UP#areset used UP#inclk0 used
HIDDEN_IS_NUMERIC IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#PLL_ENHPLL_CHECK 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1
HIDDEN_MF_PORTS MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1
HIDDEN_IF_PORTS IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#address {input 2} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0}
HIDDEN_IS_FIRST_EDIT 0
AUTO_DEVICE_FAMILY MAX10FPGA
AUTO_INCLK_INTERFACE_CLOCK_RATE 50000000
deviceFamily MAX 10
generateLegacySim false
  

Software Assignments

(none)

clk_50

clock_source v15.0


Parameters

clockFrequency 50000000
clockFrequencyKnown true
inputClockFrequency 0
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

disp_refclk

altera_clock_bridge v15.0
altpll_0 c0   disp_refclk
  in_clk


Parameters

DERIVED_CLOCK_RATE 150000000
EXPLICIT_CLOCK_RATE 0
NUM_CLOCK_OUTPUTS 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

hdmi_tx_int_n

altera_avalon_pio v15.0
master_0 master   hdmi_tx_int_n
  s1
clk_50 clk  
  clk
clk_reset  
  reset


Parameters

bitClearingEdgeCapReg true
bitModifyingOutReg false
captureEdge true
direction Input
edgeType FALLING
generateIRQ true
irqType LEVEL
resetValue 1
simDoTestBenchWiring true
simDrivenValue 0
width 1
clockRate 50000000
derived_has_tri false
derived_has_out false
derived_has_in true
derived_do_test_bench_wiring true
derived_capture true
derived_edge_type FALLING
derived_irq_type LEVEL
derived_has_irq true
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 1
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 1
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 1
DRIVEN_SIM_VALUE 0
EDGE_TYPE FALLING
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE LEVEL
RESET_VALUE 1

master_0

altera_jtag_avalon_master v15.0
clk_50 clk   master_0
  clk
clk_reset  
  clk_reset
master   opencores_i2c_0
  avalon_slave_0
master   product_info_0
  avalon_slave_0
master   alt_vip_cl_swi_0
  control
master   altpll_0
  pll_slave
master   hdmi_tx_int_n
  s1


Parameters

USE_PLI 0
PLI_PORT 50000
COMPONENT_CLOCK 0
FAST_VER 0
FIFO_DEPTHS 2
AUTO_DEVICE_FAMILY MAX10FPGA
AUTO_DEVICE 10M50DAF484C6GES
AUTO_DEVICE_SPEEDGRADE 6
deviceFamily MAX 10
generateLegacySim false
  

Software Assignments

(none)

opencores_i2c_0

opencores_i2c v9.1
master_0 master   opencores_i2c_0
  avalon_slave_0
clk_50 clk  
  clock
clk_reset  
  clock_reset


Parameters

AUTO_CLOCK_CLOCK_RATE 50000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

product_info_0

product_info v1.0
master_0 master   product_info_0
  avalon_slave_0
clk_50 clk  
  clock_reset
clk_reset  
  clock_reset_reset


Parameters

AUTO_DEVICE_FAMILY MAX10FPGA
AUTO_CLOCK_RESET_CLOCK_RATE 50000000
deviceFamily MAX 10
generateLegacySim false
  

Software Assignments

(none)

tpg_Black_1080

alt_vip_cl_tpg v15.0
altpll_0 c0   tpg_Black_1080
  main_clock
clk_50 clk_reset  
  main_reset
dout   alt_vip_cl_swi_0
  din5


Parameters

FAMILY MAX10FPGA
BPS 8
PIXELS_IN_PARALLEL 1
MAX_WIDTH 1920
MAX_HEIGHT 1080
OUTPUT_FORMAT 4.4.4
COLOR_SPACE RGB
INTERLACING prog
PATTERN uniform
UNIFORM_VALUE_RY 0
UNIFORM_VALUE_GCB 0
UNIFORM_VALUE_BCR 0
COLOR_PLANES_ARE_IN_PARALLEL 1
RUNTIME_CONTROL 0
AUTO_DEVICE 10M50DAF484C6GES
AUTO_DEVICE_SPEEDGRADE 6
AUTO_MAIN_CLOCK_CLOCK_RATE 150000000
AUTO_MAIN_CLOCK_CLOCK_DOMAIN 1
AUTO_MAIN_CLOCK_RESET_DOMAIN 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

tpg_Blue_1080

alt_vip_cl_tpg v15.0
altpll_0 c0   tpg_Blue_1080
  main_clock
clk_50 clk_reset  
  main_reset
dout   alt_vip_cl_swi_0
  din3


Parameters

FAMILY MAX10FPGA
BPS 8
PIXELS_IN_PARALLEL 1
MAX_WIDTH 1920
MAX_HEIGHT 1080
OUTPUT_FORMAT 4.4.4
COLOR_SPACE RGB
INTERLACING prog
PATTERN uniform
UNIFORM_VALUE_RY 0
UNIFORM_VALUE_GCB 0
UNIFORM_VALUE_BCR 255
COLOR_PLANES_ARE_IN_PARALLEL 1
RUNTIME_CONTROL 0
AUTO_DEVICE 10M50DAF484C6GES
AUTO_DEVICE_SPEEDGRADE 6
AUTO_MAIN_CLOCK_CLOCK_RATE 150000000
AUTO_MAIN_CLOCK_CLOCK_DOMAIN 1
AUTO_MAIN_CLOCK_RESET_DOMAIN 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

tpg_CB_1080

alt_vip_cl_tpg v15.0
altpll_0 c0   tpg_CB_1080
  main_clock
clk_50 clk_reset  
  main_reset
dout   alt_vip_cl_swi_0
  din0


Parameters

FAMILY MAX10FPGA
BPS 8
PIXELS_IN_PARALLEL 1
MAX_WIDTH 1920
MAX_HEIGHT 1080
OUTPUT_FORMAT 4.4.4
COLOR_SPACE RGB
INTERLACING prog
PATTERN colorbars
UNIFORM_VALUE_RY 16
UNIFORM_VALUE_GCB 16
UNIFORM_VALUE_BCR 16
COLOR_PLANES_ARE_IN_PARALLEL 1
RUNTIME_CONTROL 0
AUTO_DEVICE 10M50DAF484C6GES
AUTO_DEVICE_SPEEDGRADE 6
AUTO_MAIN_CLOCK_CLOCK_RATE 150000000
AUTO_MAIN_CLOCK_CLOCK_DOMAIN 1
AUTO_MAIN_CLOCK_RESET_DOMAIN 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

tpg_Green_1080

alt_vip_cl_tpg v15.0
altpll_0 c0   tpg_Green_1080
  main_clock
clk_50 clk_reset  
  main_reset
dout   alt_vip_cl_swi_0
  din2


Parameters

FAMILY MAX10FPGA
BPS 8
PIXELS_IN_PARALLEL 1
MAX_WIDTH 1920
MAX_HEIGHT 1080
OUTPUT_FORMAT 4.4.4
COLOR_SPACE RGB
INTERLACING prog
PATTERN uniform
UNIFORM_VALUE_RY 0
UNIFORM_VALUE_GCB 255
UNIFORM_VALUE_BCR 0
COLOR_PLANES_ARE_IN_PARALLEL 1
RUNTIME_CONTROL 0
AUTO_DEVICE 10M50DAF484C6GES
AUTO_DEVICE_SPEEDGRADE 6
AUTO_MAIN_CLOCK_CLOCK_RATE 150000000
AUTO_MAIN_CLOCK_CLOCK_DOMAIN 1
AUTO_MAIN_CLOCK_RESET_DOMAIN 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

tpg_Red_1080

alt_vip_cl_tpg v15.0
altpll_0 c0   tpg_Red_1080
  main_clock
clk_50 clk_reset  
  main_reset
dout   alt_vip_cl_swi_0
  din1


Parameters

FAMILY MAX10FPGA
BPS 8
PIXELS_IN_PARALLEL 1
MAX_WIDTH 1920
MAX_HEIGHT 1080
OUTPUT_FORMAT 4.4.4
COLOR_SPACE RGB
INTERLACING prog
PATTERN uniform
UNIFORM_VALUE_RY 255
UNIFORM_VALUE_GCB 0
UNIFORM_VALUE_BCR 0
COLOR_PLANES_ARE_IN_PARALLEL 1
RUNTIME_CONTROL 0
AUTO_DEVICE 10M50DAF484C6GES
AUTO_DEVICE_SPEEDGRADE 6
AUTO_MAIN_CLOCK_CLOCK_RATE 150000000
AUTO_MAIN_CLOCK_CLOCK_DOMAIN 1
AUTO_MAIN_CLOCK_RESET_DOMAIN 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

tpg_White_1080

alt_vip_cl_tpg v15.0
altpll_0 c0   tpg_White_1080
  main_clock
clk_50 clk_reset  
  main_reset
dout   alt_vip_cl_swi_0
  din4


Parameters

FAMILY MAX10FPGA
BPS 8
PIXELS_IN_PARALLEL 1
MAX_WIDTH 1920
MAX_HEIGHT 1080
OUTPUT_FORMAT 4.4.4
COLOR_SPACE RGB
INTERLACING prog
PATTERN uniform
UNIFORM_VALUE_RY 255
UNIFORM_VALUE_GCB 255
UNIFORM_VALUE_BCR 255
COLOR_PLANES_ARE_IN_PARALLEL 1
RUNTIME_CONTROL 0
AUTO_DEVICE 10M50DAF484C6GES
AUTO_DEVICE_SPEEDGRADE 6
AUTO_MAIN_CLOCK_CLOCK_RATE 150000000
AUTO_MAIN_CLOCK_CLOCK_DOMAIN 1
AUTO_MAIN_CLOCK_RESET_DOMAIN 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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