q_sys

2015.03.25.13:55:59 Datasheet
Overview
  mSGDMA_0_clk  q_sys
  mSGDMA_0_clk_0 
  sys_clk 

All Components
   mSGDMA_0 mSGDMA 1.0
   mSGDMA_0_dispatcher_read modular_sgdma_dispatcher 15.0
   mSGDMA_0_dispatcher_write modular_sgdma_dispatcher 15.0
   mSGDMA_0_freq_counter_0 freq_counter 1.0
   mSGDMA_0_mm_bridge_slv altera_avalon_mm_bridge 15.0
   mSGDMA_0_prbs_pattern_checker prbs_pattern_checker 1.1
   mSGDMA_0_prbs_pattern_generator prbs_pattern_generator 1.1
   mSGDMA_0_status_mon_0 status_mon 1.0
   mSGDMA_0_timer_0 altera_avalon_timer 15.0
   master_driver_msgdma_0 master_driver_msgdma 1.0
   mem_if_ddr3_emif_0 altera_mem_if_ddr3_emif 15.0
   product_info_0 product_info 1.0
Memory Map
mSGDMA_0 mSGDMA_0_dma_read_master mSGDMA_0_dma_write_master master_0 master_driver_msgdma_0
 dma_read_master  dma_write_master  Data_Read_Master  Data_Write_Master  master  avalon_master
  mSGDMA_0
mm_bridge_slv 
  mSGDMA_0_dispatcher_read
CSR  0x00200080
Descriptor_Slave  0x002000b0
  mSGDMA_0_dispatcher_write
CSR  0x00200060
Descriptor_Slave  0x002000a0
  mSGDMA_0_freq_counter_0
csr  0x00290000
  mSGDMA_0_prbs_pattern_checker
csr  0x00200000
  mSGDMA_0_prbs_pattern_generator
csr  0x00200040
  mSGDMA_0_status_mon_0
slv  0x00281200
  mSGDMA_0_timer_0
s1  0x00281000
  master_driver_msgdma_0
csr  0x00100000
  mem_if_ddr3_emif_0
avl  0x00000000 0x00000000 0x00000000 0x00000000
csr 
  product_info_0
avalon_slave_0  0x00000000

mSGDMA_0

mSGDMA v1.0


Parameters

AUTO_GENERATION_ID 1427262958
AUTO_UNIQUE_ID q_sys_mSGDMA_0
AUTO_DEVICE_FAMILY MAX10FPGA
AUTO_DEVICE 10M50DAF484C6GES
AUTO_DEVICE_SPEEDGRADE 6
AUTO_CLK_CLOCK_RATE 150000000
AUTO_CLK_CLOCK_DOMAIN 2
AUTO_CLK_RESET_DOMAIN 2
AUTO_CLK_0_CLOCK_RATE 50000000
AUTO_CLK_0_CLOCK_DOMAIN 4
AUTO_CLK_0_RESET_DOMAIN 4
AUTO_DMA_READ_MASTER_ADDRESS_MAP <address-map><slave name='mem_if_ddr3_emif_0.avl' start='0x0' end='0x8000000' /></address-map>
AUTO_DMA_READ_MASTER_ADDRESS_WIDTH com.altera.entityinterfaces.moduleext.AddressWidthType@121809f3
AUTO_DMA_WRITE_MASTER_ADDRESS_MAP <address-map><slave name='mem_if_ddr3_emif_0.avl' start='0x0' end='0x8000000' /></address-map>
AUTO_DMA_WRITE_MASTER_ADDRESS_WIDTH com.altera.entityinterfaces.moduleext.AddressWidthType@737da958
deviceFamily MAX 10
generateLegacySim false
  

Software Assignments

(none)

mSGDMA_0_clk

clock_source v15.0
mem_if_ddr3_emif_0 afi_clk   mSGDMA_0_clk
  clk_in
afi_reset  
  clk_in_reset
master_driver_msgdma_0 reset_source  
  clk_in_reset
clk   mSGDMA_0_dma_read_master
  Clock
clk_reset  
  Clock_reset
clk   mSGDMA_0_dma_write_master
  Clock
clk_reset  
  Clock_reset
clk   mSGDMA_0_timing_adapter
  clk
clk_reset  
  reset
clk   mSGDMA_0_mm_bridge_slv
  clk
clk_reset  
  reset
clk   mSGDMA_0_dispatcher_read
  clock
clk_reset  
  clock_reset
clk   mSGDMA_0_prbs_pattern_checker
  clock
clk_reset  
  reset
clk   mSGDMA_0_dispatcher_write
  clock
clk_reset  
  clock_reset
clk   mSGDMA_0_prbs_pattern_generator
  clock
clk_reset  
  reset
clk   mSGDMA_0_status_mon_0
  clock
clk_reset  
  reset_n
clk   mSGDMA_0_freq_counter_0
  sample_clock
clk_reset   mSGDMA_0_timer_0
  reset


Parameters

clockFrequency 150000000
clockFrequencyKnown true
inputClockFrequency 150000000
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

mSGDMA_0_clk_0

clock_source v15.0
sys_clk clk   mSGDMA_0_clk_0
  clk_in
clk_reset  
  clk_in_reset
clk   mSGDMA_0_timer_0
  clk
clk   mSGDMA_0_freq_counter_0
  clock
clk_reset  
  reset


Parameters

clockFrequency 50000000
clockFrequencyKnown true
inputClockFrequency 50000000
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

mSGDMA_0_dispatcher_read

modular_sgdma_dispatcher v15.0
mSGDMA_0_mm_bridge_slv m0   mSGDMA_0_dispatcher_read
  CSR
m0  
  Descriptor_Slave
mSGDMA_0_dma_read_master Response_Source  
  Read_Response_Sink
mSGDMA_0_clk clk  
  clock
clk_reset  
  clock_reset
master_driver_msgdma_0 interrupt_receiver  
  csr_irq
Read_Command_Source   mSGDMA_0_dma_read_master
  Command_Sink


Parameters

MODE 1
GUI_RESPONSE_PORT 0
RESPONSE_PORT 2
DESCRIPTOR_FIFO_DEPTH 1024
ENHANCED_FEATURES 0
DESCRIPTOR_WIDTH 128
DESCRIPTOR_BYTEENABLE_WIDTH 16
CSR_ADDRESS_WIDTH 3
DATA_WIDTH 32
DATA_FIFO_DEPTH 32
MAX_BYTE 1024
TRANSFER_TYPE Aligned Accesses
BURST_ENABLE 0
MAX_BURST_COUNT 2
BURST_WRAPPING_SUPPORT 0
STRIDE_ENABLE 0
MAX_STRIDE 1
PROGRAMMABLE_BURST_ENABLE 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BURST_ENABLE 0
BURST_WRAPPING_SUPPORT 0
DATA_FIFO_DEPTH 32
DATA_WIDTH 32
DESCRIPTOR_FIFO_DEPTH 1024
ENHANCED_FEATURES 0
MAX_BURST_COUNT 2
MAX_BYTE 1024
MAX_STRIDE 1
PROGRAMMABLE_BURST_ENABLE 0
RESPONSE_FIFO_DEPTH 2048
RESPONSE_PORT 0
STRIDE_ENABLE 0
TRANSFER_TYPE Aligned Accesses

mSGDMA_0_dispatcher_write

modular_sgdma_dispatcher v15.0
mSGDMA_0_mm_bridge_slv m0   mSGDMA_0_dispatcher_write
  CSR
m0  
  Descriptor_Slave
mSGDMA_0_dma_write_master Response_Source  
  Write_Response_Sink
mSGDMA_0_clk clk  
  clock
clk_reset  
  clock_reset
master_driver_msgdma_0 interrupt_receiver  
  csr_irq
Write_Command_Source   mSGDMA_0_dma_write_master
  Command_Sink


Parameters

MODE 2
GUI_RESPONSE_PORT 2
RESPONSE_PORT 2
DESCRIPTOR_FIFO_DEPTH 1024
ENHANCED_FEATURES 0
DESCRIPTOR_WIDTH 128
DESCRIPTOR_BYTEENABLE_WIDTH 16
CSR_ADDRESS_WIDTH 3
DATA_WIDTH 32
DATA_FIFO_DEPTH 32
MAX_BYTE 1024
TRANSFER_TYPE Aligned Accesses
BURST_ENABLE 0
MAX_BURST_COUNT 2
BURST_WRAPPING_SUPPORT 0
STRIDE_ENABLE 0
MAX_STRIDE 1
PROGRAMMABLE_BURST_ENABLE 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BURST_ENABLE 0
BURST_WRAPPING_SUPPORT 0
DATA_FIFO_DEPTH 32
DATA_WIDTH 32
DESCRIPTOR_FIFO_DEPTH 1024
ENHANCED_FEATURES 0
MAX_BURST_COUNT 2
MAX_BYTE 1024
MAX_STRIDE 1
PROGRAMMABLE_BURST_ENABLE 0
RESPONSE_FIFO_DEPTH 2048
RESPONSE_PORT 2
STRIDE_ENABLE 0
TRANSFER_TYPE Aligned Accesses

mSGDMA_0_dma_read_master

dma_read_master v15.0
mSGDMA_0_dispatcher_read Read_Command_Source   mSGDMA_0_dma_read_master
  Command_Sink
mSGDMA_0_clk clk  
  Clock
clk_reset  
  Clock_reset
Data_Source   mSGDMA_0_prbs_pattern_checker
  st_pattern_input
Response_Source   mSGDMA_0_dispatcher_read
  Read_Response_Sink
Data_Read_Master   mem_if_ddr3_emif_0
  avl


Parameters

DATA_WIDTH 128
LENGTH_WIDTH 31
FIFO_DEPTH 1024
STRIDE_ENABLE 0
GUI_STRIDE_WIDTH 1
BURST_ENABLE 1
GUI_MAX_BURST_COUNT 32
GUI_PROGRAMMABLE_BURST_ENABLE 0
GUI_BURST_WRAPPING_SUPPORT 0
TRANSFER_TYPE Full Word Accesses Only
PACKET_ENABLE 0
ERROR_ENABLE 0
ERROR_WIDTH 8
CHANNEL_ENABLE 0
CHANNEL_WIDTH 8
BYTE_ENABLE_WIDTH 16
BYTE_ENABLE_WIDTH_LOG2 4
ADDRESS_WIDTH 27
FIFO_DEPTH_LOG2 10
SYMBOL_WIDTH 8
NUMBER_OF_SYMBOLS 16
NUMBER_OF_SYMBOLS_LOG2 4
MAX_BURST_COUNT_WIDTH 6
UNALIGNED_ACCESSES_ENABLE 0
ONLY_FULL_ACCESS_ENABLE 1
BURST_WRAPPING_SUPPORT 0
PROGRAMMABLE_BURST_ENABLE 0
MAX_BURST_COUNT 32
FIFO_SPEED_OPTIMIZATION 1
STRIDE_WIDTH 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

mSGDMA_0_dma_write_master

dma_write_master v15.0
mSGDMA_0_dispatcher_write Write_Command_Source   mSGDMA_0_dma_write_master
  Command_Sink
mSGDMA_0_timing_adapter out  
  Data_Sink
mSGDMA_0_clk clk  
  Clock
clk_reset  
  Clock_reset
Response_Source   mSGDMA_0_dispatcher_write
  Write_Response_Sink
Data_Write_Master   mem_if_ddr3_emif_0
  avl


Parameters

DATA_WIDTH 128
LENGTH_WIDTH 31
FIFO_DEPTH 1024
STRIDE_ENABLE 0
GUI_STRIDE_WIDTH 1
BURST_ENABLE 1
GUI_MAX_BURST_COUNT 32
GUI_PROGRAMMABLE_BURST_ENABLE 0
GUI_BURST_WRAPPING_SUPPORT 0
TRANSFER_TYPE Full Word Accesses Only
PACKET_ENABLE 0
ERROR_ENABLE 0
ERROR_WIDTH 8
BYTE_ENABLE_WIDTH 16
BYTE_ENABLE_WIDTH_LOG2 4
ADDRESS_WIDTH 27
FIFO_DEPTH_LOG2 10
SYMBOL_WIDTH 8
NUMBER_OF_SYMBOLS 16
NUMBER_OF_SYMBOLS_LOG2 4
MAX_BURST_COUNT_WIDTH 6
UNALIGNED_ACCESSES_ENABLE 0
ONLY_FULL_ACCESS_ENABLE 1
BURST_WRAPPING_SUPPORT 0
PROGRAMMABLE_BURST_ENABLE 0
MAX_BURST_COUNT 32
FIFO_SPEED_OPTIMIZATION 1
STRIDE_WIDTH 1
ACTUAL_BYTES_TRANSFERRED_WIDTH 32
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

mSGDMA_0_freq_counter_0

freq_counter v1.0
mSGDMA_0_mm_bridge_slv m0   mSGDMA_0_freq_counter_0
  csr
mSGDMA_0_clk_0 clk  
  clock
clk_reset  
  reset
mSGDMA_0_clk clk  
  sample_clock


Parameters

SYSTEM_CLK_FREQ_PICO_SEC 20000
DIV 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

mSGDMA_0_mm_bridge_slv

altera_avalon_mm_bridge v15.0
mSGDMA_0_clk clk   mSGDMA_0_mm_bridge_slv
  clk
clk_reset  
  reset
master_driver_msgdma_0 avalon_master  
  s0
m0   mSGDMA_0_dispatcher_write
  CSR
m0  
  Descriptor_Slave
m0   mSGDMA_0_dispatcher_read
  CSR
m0  
  Descriptor_Slave
m0   mSGDMA_0_prbs_pattern_generator
  csr
m0   mSGDMA_0_prbs_pattern_checker
  csr
m0   mSGDMA_0_freq_counter_0
  csr
m0   mSGDMA_0_timer_0
  s1
m0   mSGDMA_0_status_mon_0
  slv


Parameters

DATA_WIDTH 32
SYMBOL_WIDTH 8
ADDRESS_WIDTH 20
SYSINFO_ADDR_WIDTH 20
USE_AUTO_ADDRESS_WIDTH 0
AUTO_ADDRESS_WIDTH 20
HDL_ADDR_WIDTH 20
ADDRESS_UNITS SYMBOLS
BURSTCOUNT_WIDTH 7
MAX_BURST_SIZE 64
MAX_PENDING_RESPONSES 16
LINEWRAPBURSTS 0
PIPELINE_COMMAND 1
PIPELINE_RESPONSE 1
USE_RESPONSE 0
AUTO_DEVICE_FAMILY MAX10FPGA
AUTO_CLK_CLOCK_RATE 150000000
deviceFamily MAX 10
generateLegacySim false
  

Software Assignments

(none)

mSGDMA_0_prbs_pattern_checker

prbs_pattern_checker v1.1
mSGDMA_0_mm_bridge_slv m0   mSGDMA_0_prbs_pattern_checker
  csr
mSGDMA_0_dma_read_master Data_Source  
  st_pattern_input
mSGDMA_0_clk clk  
  clock
clk_reset  
  reset


Parameters

DATA_WIDTH 128
PRBS_WIDTH 16
AUTO_CLOCK_CLOCK_RATE 150000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

mSGDMA_0_prbs_pattern_generator

prbs_pattern_generator v1.1
mSGDMA_0_mm_bridge_slv m0   mSGDMA_0_prbs_pattern_generator
  csr
mSGDMA_0_clk clk  
  clock
clk_reset  
  reset
st_pattern_output   mSGDMA_0_timing_adapter
  in


Parameters

DATA_WIDTH 128
PRBS_WIDTH 16
AUTO_CLOCK_CLOCK_RATE 150000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

mSGDMA_0_status_mon_0

status_mon v1.0
mSGDMA_0_mm_bridge_slv m0   mSGDMA_0_status_mon_0
  slv
mSGDMA_0_clk clk  
  clock
clk_reset  
  reset_n
status   mem_if_ddr3_emif_0
  status


Parameters

deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

mSGDMA_0_timer_0

altera_avalon_timer v15.0
mSGDMA_0_mm_bridge_slv m0   mSGDMA_0_timer_0
  s1
mSGDMA_0_clk_0 clk  
  clk
mSGDMA_0_clk clk_reset  
  reset


Parameters

alwaysRun false
counterSize 32
fixedPeriod false
period 1
periodUnits MSEC
resetOutput false
snapshot true
timeoutPulseOutput false
systemFrequency 50000000
watchdogPulse 2
timerPreset FULL_FEATURED
periodUnitsString ms
valueInSecond 0
loadValue 49999
mult 0
ticksPerSec 1000
slave_address_width 3
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ALWAYS_RUN 0
COUNTER_SIZE 32
FIXED_PERIOD 0
FREQ 50000000
LOAD_VALUE 49999
MULT 0.001
PERIOD 1
PERIOD_UNITS ms
RESET_OUTPUT 0
SNAPSHOT 1
TICKS_PER_SEC 1000
TIMEOUT_PULSE_OUTPUT 0

mSGDMA_0_timing_adapter

timing_adapter v15.0
mSGDMA_0_prbs_pattern_generator st_pattern_output   mSGDMA_0_timing_adapter
  in
mSGDMA_0_clk clk  
  clk
clk_reset  
  reset
out   mSGDMA_0_dma_write_master
  Data_Sink


Parameters

inChannelWidth 0
inMaxChannel 0
inBitsPerSymbol 8
inUsePackets false
inUseEmptyPort AUTO
inUseEmpty false
inSymbolsPerBeat 16
inUseReady true
outUseReady true
inReadyLatency 1
outReadyLatency 0
inErrorWidth 0
inErrorDescriptor
inUseValid true
outUseValid true
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

master_0

altera_jtag_avalon_master v15.0
sys_clk clk   master_0
  clk
clk_reset  
  clk_reset
master   product_info_0
  avalon_slave_0
master   master_driver_msgdma_0
  csr


Parameters

USE_PLI 0
PLI_PORT 50000
COMPONENT_CLOCK 0
FAST_VER 0
FIFO_DEPTHS 2
AUTO_DEVICE_FAMILY MAX10FPGA
AUTO_DEVICE 10M50DAF484C6GES
AUTO_DEVICE_SPEEDGRADE 6
deviceFamily MAX 10
generateLegacySim false
  

Software Assignments

(none)

master_driver_msgdma_0

master_driver_msgdma v1.0
master_0 master   master_driver_msgdma_0
  csr
sys_clk clk  
  clock
clk_reset  
  reset
avalon_master   mSGDMA_0_mm_bridge_slv
  s0
interrupt_receiver   mSGDMA_0_dispatcher_read
  csr_irq
interrupt_receiver   mSGDMA_0_dispatcher_write
  csr_irq
reset_source   mSGDMA_0_clk
  clk_in_reset


Parameters

PRBS_PATTERN_GENERATOR_BASE 2097216
PRBS_PATTERN_CHECKER_BASE 2097152
MEMORY_BASE_ADDRESS 0
MEMORY_SPAN 67108864
BLOCK_SIZE 67108864
DISPATCHER_WRITE_CSR 2097248
DISPATCHER_WRITE_DESCRIPTOR 2097312
DISPATCHER_READ_CSR 2097280
DISPATCHER_READ_DESCRIPTOR 2097328
TIMER_BASE 2625536
FREQUENCY_COUNTER_BASE 2686976
ENABLE_PER_INFO 1
LOCAL_DATA_WORDS 8
AUTO_INTERRUPT_RECEIVER_INTERRUPTS_USED 3
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

mem_if_ddr3_emif_0

altera_mem_if_ddr3_emif v15.0
mSGDMA_0_dma_read_master Data_Read_Master   mem_if_ddr3_emif_0
  avl
mSGDMA_0_dma_write_master Data_Write_Master  
  avl
sys_clk clk  
  pll_ref_clk
clk_reset  
  global_reset
clk_reset  
  soft_reset
mSGDMA_0_status_mon_0 status  
  status
afi_clk   mSGDMA_0_clk
  clk_in
afi_reset  
  clk_in_reset


Parameters

AC_ROM_MR0 0001000010001
AC_ROM_MR0_MIRR 0001000001001
AC_ROM_MR0_CALIB
AC_ROM_MR0_DLL_RESET 0001100010000
AC_ROM_MR0_DLL_RESET_MIRR 0001010001000
AC_ROM_MR1 0000000000000
AC_ROM_MR1_MIRR 0000000000000
AC_ROM_MR1_CALIB
AC_ROM_MR1_OCD_ENABLE
AC_ROM_MR2 0000000000000
AC_ROM_MR2_MIRR 0000000000000
AC_ROM_MR3 0000000000000
AC_ROM_MR3_MIRR 0000000000000
USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY false
MR0_BL 1
MR0_BT 0
MR0_CAS_LATENCY 1
MR0_DLL 1
MR0_WR 1
MR0_PD 0
MR1_DLL 0
MR1_ODS 0
MR1_RTT 0
MR1_AL 0
MR1_WL 0
MR1_TDQS 0
MR1_QOFF 0
MR1_DQS 0
MR1_RDQS 0
MR2_CWL 0
MR2_ASR 0
MR2_SRT 0
MR2_SRF 0
MR2_RTT_WR 0
MR3_MPR_RF 0
MR3_MPR 0
MR3_MPR_AA 0
MEM_IF_READ_DQS_WIDTH 3
MEM_IF_WRITE_DQS_WIDTH 3
SCC_DATA_WIDTH 1
MEM_IF_ADDR_WIDTH 13
MEM_IF_ADDR_WIDTH_MIN 13
MEM_IF_ROW_ADDR_WIDTH 13
MEM_IF_COL_ADDR_WIDTH 10
MEM_IF_DM_WIDTH 3
MEM_IF_CS_PER_RANK 1
MEM_IF_NUMBER_OF_RANKS 1
MEM_IF_CS_PER_DIMM 1
MEM_IF_CONTROL_WIDTH 1
MEM_BURST_LENGTH 8
MEM_LEVELING true
MEM_IF_DQS_WIDTH 3
MEM_IF_CS_WIDTH 1
MEM_IF_CHIP_BITS 1
MEM_IF_BANKADDR_WIDTH 3
MEM_IF_DQ_WIDTH 24
MEM_IF_CK_WIDTH 1
MEM_IF_CLK_EN_WIDTH 1
MEM_IF_CLK_PAIR_COUNT 1
DEVICE_WIDTH 1
MEM_CLK_MAX_NS 1.25
MEM_CLK_MAX_PS 1250.0
MEM_TRC 15
MEM_TRAS 11
MEM_TRCD 5
MEM_TRP 5
MEM_TREFI 2341
MEM_TRFC 34
CFG_TCCD 1
MEM_TWR 5
MEM_TFAW 10
MEM_TRRD 2
MEM_TRTP 3
MEM_DQS_TO_CLK_CAPTURE_DELAY 100
MEM_CLK_TO_DQS_CAPTURE_DELAY 100000
MEM_IF_ODT_WIDTH 1
MEM_WTCL_INT 5
FLY_BY true
RDIMM false
LRDIMM false
RDIMM_INT 0
LRDIMM_INT 0
MEM_IF_LRDIMM_RM 0
MEM_IF_RD_TO_WR_TURNAROUND_OCT 2
MEM_IF_WR_TO_RD_TURNAROUND_OCT 3
CTL_RD_TO_PCH_EXTRA_CLK 0
CTL_RD_TO_RD_EXTRA_CLK 0
CTL_WR_TO_WR_EXTRA_CLK 0
CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK 1
CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK 1
MEM_TYPE DDR3
MEM_MIRROR_ADDRESSING_DEC 0
MEM_ATCL_INT 0
MEM_REGDIMM_ENABLED false
MEM_LRDIMM_ENABLED false
MEM_VENDOR JEDEC
MEM_FORMAT DISCRETE
AC_PARITY false
RDIMM_CONFIG 0000000000000000
LRDIMM_EXTENDED_CONFIG 0x000000000000000000
DISCRETE_FLY_BY true
DEVICE_DEPTH 1
MEM_MIRROR_ADDRESSING 0
MEM_CLK_FREQ_MAX 800.0
MEM_ROW_ADDR_WIDTH 13
MEM_COL_ADDR_WIDTH 10
MEM_DQ_WIDTH 24
MEM_DQ_PER_DQS 8
MEM_BANKADDR_WIDTH 3
MEM_IF_DM_PINS_EN true
MEM_IF_DQSN_EN true
MEM_NUMBER_OF_DIMMS 1
MEM_NUMBER_OF_RANKS_PER_DIMM 1
MEM_NUMBER_OF_RANKS_PER_DEVICE 1
MEM_RANK_MULTIPLICATION_FACTOR 1
MEM_CK_WIDTH 1
MEM_CS_WIDTH 1
MEM_CLK_EN_WIDTH 1
ALTMEMPHY_COMPATIBLE_MODE false
NEXTGEN true
MEM_IF_BOARD_BASE_DELAY 10
MEM_IF_SIM_VALID_WINDOW 0
MEM_GUARANTEED_WRITE_INIT false
MEM_VERBOSE true
PINGPONGPHY_EN false
DUPLICATE_AC false
REFRESH_BURST_VALIDATION false
AP_MODE_EN 0
AP_MODE false
MEM_BL OTF
MEM_BT Sequential
MEM_ASR Manual
MEM_SRT Normal
MEM_PD DLL off
MEM_DRV_STR RZQ/6
MEM_DLL_EN true
MEM_RTT_NOM ODT Disabled
MEM_RTT_WR Dynamic ODT off
MEM_WTCL 5
MEM_ATCL Disabled
MEM_TCL 5
MEM_AUTO_LEVELING_MODE true
MEM_USER_LEVELING_MODE Leveling
MEM_INIT_EN false
MEM_INIT_FILE
DAT_DATA_WIDTH 32
TIMING_TIS 170
TIMING_TIH 120
TIMING_TDS 10
TIMING_TDH 45
TIMING_TDQSQ 100
TIMING_TQH 0.38
TIMING_TDQSCK 225
TIMING_TDQSCKDS 450
TIMING_TDQSCKDM 900
TIMING_TDQSCKDL 1200
TIMING_TDQSS 0.27
TIMING_TQSH 0.4
TIMING_TDSH 0.18
TIMING_TDSS 0.18
MEM_TINIT_US 500
MEM_TINIT_CK 150000
MEM_TDQSCK 1
MEM_TMRD_CK 4
MEM_TRAS_NS 35.0
MEM_TRCD_NS 13.75
MEM_TRP_NS 13.75
MEM_TREFI_US 7.8
MEM_TRFC_NS 110.0
CFG_TCCD_NS 2.5
MEM_TWR_NS 15.0
MEM_TWTR 6
MEM_TFAW_NS 30.0
MEM_TRRD_NS 6.0
MEM_TRTP_NS 7.5
RATE Half
MEM_CLK_FREQ 300.0
USE_MEM_CLK_FREQ false
USE_DQS_TRACKING false
FORCE_DQS_TRACKING AUTO
USE_HPS_DQS_TRACKING false
TRK_PARALLEL_SCC_LOAD false
USE_SHADOW_REGS false
FORCE_SHADOW_REGS AUTO
DQ_DDR 1
ADDR_CMD_DDR 0
AFI_RATE_RATIO 2
DATA_RATE_RATIO 2
ADDR_RATE_RATIO 1
AFI_ADDR_WIDTH 26
AFI_BANKADDR_WIDTH 6
AFI_CONTROL_WIDTH 2
AFI_CS_WIDTH 2
AFI_CLK_EN_WIDTH 2
AFI_DM_WIDTH 12
AFI_DQ_WIDTH 96
AFI_ODT_WIDTH 2
AFI_WRITE_DQS_WIDTH 6
AFI_RLAT_WIDTH 6
AFI_WLAT_WIDTH 6
AFI_RRANK_WIDTH 6
AFI_WRANK_WIDTH 6
AFI_CLK_PAIR_COUNT 1
MRS_MIRROR_PING_PONG_ATSO false
SYS_INFO_DEVICE_FAMILY MAX10FPGA
PARSE_FRIENDLY_DEVICE_FAMILY MAX10
DEVICE_FAMILY MAX 10
PRE_V_SERIES_FAMILY true
PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID true
PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID false
PARSE_FRIENDLY_DEVICE_FAMILY_PARAM
DEVICE_FAMILY_PARAM
SPEED_GRADE 6
IS_ES_DEVICE false
DISABLE_CHILD_MESSAGING false
HARD_PHY false
HARD_EMIF false
HHP_HPS false
HHP_HPS_VERIFICATION false
HHP_HPS_SIMULATION false
HPS_PROTOCOL DEFAULT
CUT_NEW_FAMILY_TIMING true
EXPORT_CSR_PORT false
CSR_ADDR_WIDTH 8
CSR_DATA_WIDTH 32
CSR_BE_WIDTH 4
CTL_CS_WIDTH 1
AVL_ADDR_WIDTH 24
AVL_BE_WIDTH 8
AVL_DATA_WIDTH 64
AVL_SYMBOL_WIDTH 8
AVL_NUM_SYMBOLS 8
AVL_SIZE_WIDTH 3
HR_DDIO_OUT_HAS_THREE_REGS false
CTL_ECC_CSR_ENABLED true
DWIDTH_RATIO 4
CTL_ODT_ENABLED false
CTL_OUTPUT_REGD false
CTL_ECC_MULTIPLES_40_72 1
CTL_ECC_MULTIPLES_16_24_40_72 1
CTL_REGDIMM_ENABLED false
LOW_LATENCY false
CONTROLLER_TYPE nextgen_v110
CTL_TBP_NUM 4
CTL_USR_REFRESH 0
CTL_SELF_REFRESH 0
CFG_TYPE 2
CFG_INTERFACE_WIDTH 24
CFG_BURST_LENGTH 8
CFG_ADDR_ORDER 0
CFG_PDN_EXIT_CYCLES 10
CFG_POWER_SAVING_EXIT_CYCLES 5
CFG_MEM_CLK_ENTRY_CYCLES 20
CFG_SELF_RFSH_EXIT_CYCLES 512
CFG_PORT_WIDTH_WRITE_ODT_CHIP 1
CFG_PORT_WIDTH_READ_ODT_CHIP 1
CFG_WRITE_ODT_CHIP 1
CFG_READ_ODT_CHIP 0
LOCAL_CS_WIDTH 0
CFG_CLR_INTR 0
CFG_ENABLE_NO_DM 0
MEM_ADD_LAT 0
CTL_ENABLE_BURST_INTERRUPT_INT false
CTL_ENABLE_BURST_TERMINATE_INT false
CFG_ERRCMD_FIFO_REG 0
CFG_ECC_DECODER_REG 0
CTL_ENABLE_WDATA_PATH_LATENCY false
CFG_STARVE_LIMIT 10
MEM_AUTO_PD_CYCLES 0
AVL_PORT
AVL_DATA_WIDTH_PORT_0 0
AVL_ADDR_WIDTH_PORT_0 0
PRIORITY_PORT_0 0
WEIGHT_PORT_0 0
CPORT_TYPE_PORT_0 0
AVL_NUM_SYMBOLS_PORT_0 2
LSB_WFIFO_PORT_0 5
MSB_WFIFO_PORT_0 5
LSB_RFIFO_PORT_0 5
MSB_RFIFO_PORT_0 5
AVL_DATA_WIDTH_PORT_1 0
AVL_ADDR_WIDTH_PORT_1 0
PRIORITY_PORT_1 0
WEIGHT_PORT_1 0
CPORT_TYPE_PORT_1 0
AVL_NUM_SYMBOLS_PORT_1 2
LSB_WFIFO_PORT_1 5
MSB_WFIFO_PORT_1 5
LSB_RFIFO_PORT_1 5
MSB_RFIFO_PORT_1 5
AVL_DATA_WIDTH_PORT_2 0
AVL_ADDR_WIDTH_PORT_2 0
PRIORITY_PORT_2 0
WEIGHT_PORT_2 0
CPORT_TYPE_PORT_2 0
AVL_NUM_SYMBOLS_PORT_2 2
LSB_WFIFO_PORT_2 5
MSB_WFIFO_PORT_2 5
LSB_RFIFO_PORT_2 5
MSB_RFIFO_PORT_2 5
AVL_DATA_WIDTH_PORT_3 0
AVL_ADDR_WIDTH_PORT_3 0
PRIORITY_PORT_3 0
WEIGHT_PORT_3 0
CPORT_TYPE_PORT_3 0
AVL_NUM_SYMBOLS_PORT_3 2
LSB_WFIFO_PORT_3 5
MSB_WFIFO_PORT_3 5
LSB_RFIFO_PORT_3 5
MSB_RFIFO_PORT_3 5
AVL_DATA_WIDTH_PORT_4 0
AVL_ADDR_WIDTH_PORT_4 0
PRIORITY_PORT_4 0
WEIGHT_PORT_4 0
CPORT_TYPE_PORT_4 0
AVL_NUM_SYMBOLS_PORT_4 2
LSB_WFIFO_PORT_4 5
MSB_WFIFO_PORT_4 5
LSB_RFIFO_PORT_4 5
MSB_RFIFO_PORT_4 5
AVL_DATA_WIDTH_PORT_5 0
AVL_ADDR_WIDTH_PORT_5 0
PRIORITY_PORT_5 0
WEIGHT_PORT_5 0
CPORT_TYPE_PORT_5 0
AVL_NUM_SYMBOLS_PORT_5 2
LSB_WFIFO_PORT_5 5
MSB_WFIFO_PORT_5 5
LSB_RFIFO_PORT_5 5
MSB_RFIFO_PORT_5 5
ALLOCATED_RFIFO_PORT 0,None,None,None,None,None
ALLOCATED_WFIFO_PORT 0,None,None,None,None,None
ENUM_ATTR_COUNTER_ONE_RESET DISABLED
ENUM_ATTR_COUNTER_ZERO_RESET DISABLED
ENUM_ATTR_STATIC_CONFIG_VALID DISABLED
ENUM_AUTO_PCH_ENABLE_0 DISABLED
ENUM_AUTO_PCH_ENABLE_1 DISABLED
ENUM_AUTO_PCH_ENABLE_2 DISABLED
ENUM_AUTO_PCH_ENABLE_3 DISABLED
ENUM_AUTO_PCH_ENABLE_4 DISABLED
ENUM_AUTO_PCH_ENABLE_5 DISABLED
ENUM_CAL_REQ DISABLED
ENUM_CFG_BURST_LENGTH BL_8
ENUM_CFG_INTERFACE_WIDTH DWIDTH_32
ENUM_CFG_SELF_RFSH_EXIT_CYCLES
ENUM_CFG_STARVE_LIMIT STARVE_LIMIT_32
ENUM_CFG_TYPE DDR3
ENUM_CLOCK_OFF_0 DISABLED
ENUM_CLOCK_OFF_1 DISABLED
ENUM_CLOCK_OFF_2 DISABLED
ENUM_CLOCK_OFF_3 DISABLED
ENUM_CLOCK_OFF_4 DISABLED
ENUM_CLOCK_OFF_5 DISABLED
ENUM_CLR_INTR NO_CLR_INTR
ENUM_CMD_PORT_IN_USE_0 FALSE
ENUM_CMD_PORT_IN_USE_1 FALSE
ENUM_CMD_PORT_IN_USE_2 FALSE
ENUM_CMD_PORT_IN_USE_3 FALSE
ENUM_CMD_PORT_IN_USE_4 FALSE
ENUM_CMD_PORT_IN_USE_5 FALSE
ENUM_CPORT0_RDY_ALMOST_FULL NOT_FULL
ENUM_CPORT0_RFIFO_MAP FIFO_0
ENUM_CPORT0_TYPE DISABLE
ENUM_CPORT0_WFIFO_MAP FIFO_0
ENUM_CPORT1_RDY_ALMOST_FULL NOT_FULL
ENUM_CPORT1_RFIFO_MAP FIFO_0
ENUM_CPORT1_TYPE DISABLE
ENUM_CPORT1_WFIFO_MAP FIFO_0
ENUM_CPORT2_RDY_ALMOST_FULL NOT_FULL
ENUM_CPORT2_RFIFO_MAP FIFO_0
ENUM_CPORT2_TYPE DISABLE
ENUM_CPORT2_WFIFO_MAP FIFO_0
ENUM_CPORT3_RDY_ALMOST_FULL NOT_FULL
ENUM_CPORT3_RFIFO_MAP FIFO_0
ENUM_CPORT3_TYPE DISABLE
ENUM_CPORT3_WFIFO_MAP FIFO_0
ENUM_CPORT4_RDY_ALMOST_FULL NOT_FULL
ENUM_CPORT4_RFIFO_MAP FIFO_0
ENUM_CPORT4_TYPE DISABLE
ENUM_CPORT4_WFIFO_MAP FIFO_0
ENUM_CPORT5_RDY_ALMOST_FULL NOT_FULL
ENUM_CPORT5_RFIFO_MAP FIFO_0
ENUM_CPORT5_TYPE DISABLE
ENUM_CPORT5_WFIFO_MAP FIFO_0
ENUM_CTL_ADDR_ORDER CHIP_BANK_ROW_COL
ENUM_CTL_ECC_ENABLED CTL_ECC_DISABLED
ENUM_CTL_ECC_RMW_ENABLED CTL_ECC_RMW_DISABLED
ENUM_CTL_REGDIMM_ENABLED REGDIMM_DISABLED
ENUM_CTL_USR_REFRESH CTL_USR_REFRESH_DISABLED
ENUM_CTRL_WIDTH DATA_WIDTH_64_BIT
ENUM_DELAY_BONDING BONDING_LATENCY_0
ENUM_DFX_BYPASS_ENABLE DFX_BYPASS_DISABLED
ENUM_DISABLE_MERGING MERGING_ENABLED
ENUM_ECC_DQ_WIDTH ECC_DQ_WIDTH_0
ENUM_ENABLE_ATPG DISABLED
ENUM_ENABLE_BONDING_0 DISABLED
ENUM_ENABLE_BONDING_1 DISABLED
ENUM_ENABLE_BONDING_2 DISABLED
ENUM_ENABLE_BONDING_3 DISABLED
ENUM_ENABLE_BONDING_4 DISABLED
ENUM_ENABLE_BONDING_5 DISABLED
ENUM_ENABLE_BONDING_WRAPBACK DISABLED
ENUM_ENABLE_DQS_TRACKING DISABLED
ENUM_ENABLE_ECC_CODE_OVERWRITES DISABLED
ENUM_ENABLE_FAST_EXIT_PPD DISABLED
ENUM_ENABLE_INTR DISABLED
ENUM_ENABLE_NO_DM DISABLED
ENUM_ENABLE_PIPELINEGLOBAL DISABLED
ENUM_GANGED_ARF DISABLED
ENUM_GEN_DBE GEN_DBE_DISABLED
ENUM_GEN_SBE GEN_SBE_DISABLED
ENUM_INC_SYNC FIFO_SET_2
ENUM_LOCAL_IF_CS_WIDTH ADDR_WIDTH_2
ENUM_MASK_CORR_DROPPED_INTR DISABLED
ENUM_MASK_DBE_INTR DISABLED
ENUM_MASK_SBE_INTR DISABLED
ENUM_MEM_IF_AL AL_0
ENUM_MEM_IF_BANKADDR_WIDTH ADDR_WIDTH_3
ENUM_MEM_IF_BURSTLENGTH MEM_IF_BURSTLENGTH_8
ENUM_MEM_IF_COLADDR_WIDTH ADDR_WIDTH_12
ENUM_MEM_IF_CS_PER_RANK MEM_IF_CS_PER_RANK_1
ENUM_MEM_IF_CS_WIDTH MEM_IF_CS_WIDTH_1
ENUM_MEM_IF_DQ_PER_CHIP MEM_IF_DQ_PER_CHIP_8
ENUM_MEM_IF_DQS_WIDTH DQS_WIDTH_4
ENUM_MEM_IF_DWIDTH MEM_IF_DWIDTH_32
ENUM_MEM_IF_MEMTYPE DDR3_SDRAM
ENUM_MEM_IF_ROWADDR_WIDTH ADDR_WIDTH_16
ENUM_MEM_IF_SPEEDBIN DDR3_1066_6_6_6
ENUM_MEM_IF_TCCD TCCD_4
ENUM_MEM_IF_TCL TCL_6
ENUM_MEM_IF_TCWL TCWL_5
ENUM_MEM_IF_TFAW TFAW_16
ENUM_MEM_IF_TMRD
ENUM_MEM_IF_TRAS TRAS_16
ENUM_MEM_IF_TRC TRC_22
ENUM_MEM_IF_TRCD TRCD_6
ENUM_MEM_IF_TRP TRP_6
ENUM_MEM_IF_TRRD TRRD_4
ENUM_MEM_IF_TRTP TRTP_4
ENUM_MEM_IF_TWR TWR_6
ENUM_MEM_IF_TWTR TWTR_4
ENUM_MMR_CFG_MEM_BL MP_BL_8
ENUM_OUTPUT_REGD DISABLED
ENUM_PDN_EXIT_CYCLES SLOW_EXIT
ENUM_PORT0_WIDTH PORT_64_BIT
ENUM_PORT1_WIDTH PORT_64_BIT
ENUM_PORT2_WIDTH PORT_64_BIT
ENUM_PORT3_WIDTH PORT_64_BIT
ENUM_PORT4_WIDTH PORT_64_BIT
ENUM_PORT5_WIDTH PORT_64_BIT
ENUM_PRIORITY_0_0 WEIGHT_0
ENUM_PRIORITY_0_1 WEIGHT_0
ENUM_PRIORITY_0_2 WEIGHT_0
ENUM_PRIORITY_0_3 WEIGHT_0
ENUM_PRIORITY_0_4 WEIGHT_0
ENUM_PRIORITY_0_5 WEIGHT_0
ENUM_PRIORITY_1_0 WEIGHT_0
ENUM_PRIORITY_1_1 WEIGHT_0
ENUM_PRIORITY_1_2 WEIGHT_0
ENUM_PRIORITY_1_3 WEIGHT_0
ENUM_PRIORITY_1_4 WEIGHT_0
ENUM_PRIORITY_1_5 WEIGHT_0
ENUM_PRIORITY_2_0 WEIGHT_0
ENUM_PRIORITY_2_1 WEIGHT_0
ENUM_PRIORITY_2_2 WEIGHT_0
ENUM_PRIORITY_2_3 WEIGHT_0
ENUM_PRIORITY_2_4 WEIGHT_0
ENUM_PRIORITY_2_5 WEIGHT_0
ENUM_PRIORITY_3_0 WEIGHT_0
ENUM_PRIORITY_3_1 WEIGHT_0
ENUM_PRIORITY_3_2 WEIGHT_0
ENUM_PRIORITY_3_3 WEIGHT_0
ENUM_PRIORITY_3_4 WEIGHT_0
ENUM_PRIORITY_3_5 WEIGHT_0
ENUM_PRIORITY_4_0 WEIGHT_0
ENUM_PRIORITY_4_1 WEIGHT_0
ENUM_PRIORITY_4_2 WEIGHT_0
ENUM_PRIORITY_4_3 WEIGHT_0
ENUM_PRIORITY_4_4 WEIGHT_0
ENUM_PRIORITY_4_5 WEIGHT_0
ENUM_PRIORITY_5_0 WEIGHT_0
ENUM_PRIORITY_5_1 WEIGHT_0
ENUM_PRIORITY_5_2 WEIGHT_0
ENUM_PRIORITY_5_3 WEIGHT_0
ENUM_PRIORITY_5_4 WEIGHT_0
ENUM_PRIORITY_5_5 WEIGHT_0
ENUM_PRIORITY_6_0 WEIGHT_0
ENUM_PRIORITY_6_1 WEIGHT_0
ENUM_PRIORITY_6_2 WEIGHT_0
ENUM_PRIORITY_6_3 WEIGHT_0
ENUM_PRIORITY_6_4 WEIGHT_0
ENUM_PRIORITY_6_5 WEIGHT_0
ENUM_PRIORITY_7_0 WEIGHT_0
ENUM_PRIORITY_7_1 WEIGHT_0
ENUM_PRIORITY_7_2 WEIGHT_0
ENUM_PRIORITY_7_3 WEIGHT_0
ENUM_PRIORITY_7_4 WEIGHT_0
ENUM_PRIORITY_7_5 WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_0 WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_1 WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_2 WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_3 WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_4 WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_5 WEIGHT_0
ENUM_RCFG_USER_PRIORITY_0 PRIORITY_0
ENUM_RCFG_USER_PRIORITY_1 PRIORITY_0
ENUM_RCFG_USER_PRIORITY_2 PRIORITY_0
ENUM_RCFG_USER_PRIORITY_3 PRIORITY_0
ENUM_RCFG_USER_PRIORITY_4 PRIORITY_0
ENUM_RCFG_USER_PRIORITY_5 PRIORITY_0
ENUM_RD_DWIDTH_0 DWIDTH_0
ENUM_RD_DWIDTH_1 DWIDTH_0
ENUM_RD_DWIDTH_2 DWIDTH_0
ENUM_RD_DWIDTH_3 DWIDTH_0
ENUM_RD_DWIDTH_4 DWIDTH_0
ENUM_RD_DWIDTH_5 DWIDTH_0
ENUM_RD_FIFO_IN_USE_0 FALSE
ENUM_RD_FIFO_IN_USE_1 FALSE
ENUM_RD_FIFO_IN_USE_2 FALSE
ENUM_RD_FIFO_IN_USE_3 FALSE
ENUM_RD_PORT_INFO_0 USE_NO
ENUM_RD_PORT_INFO_1 USE_NO
ENUM_RD_PORT_INFO_2 USE_NO
ENUM_RD_PORT_INFO_3 USE_NO
ENUM_RD_PORT_INFO_4 USE_NO
ENUM_RD_PORT_INFO_5 USE_NO
ENUM_READ_ODT_CHIP ODT_DISABLED
ENUM_REORDER_DATA DATA_REORDERING
ENUM_RFIFO0_CPORT_MAP CMD_PORT_0
ENUM_RFIFO1_CPORT_MAP CMD_PORT_0
ENUM_RFIFO2_CPORT_MAP CMD_PORT_0
ENUM_RFIFO3_CPORT_MAP CMD_PORT_0
ENUM_SINGLE_READY_0 CONCATENATE_RDY
ENUM_SINGLE_READY_1 CONCATENATE_RDY
ENUM_SINGLE_READY_2 CONCATENATE_RDY
ENUM_SINGLE_READY_3 CONCATENATE_RDY
ENUM_STATIC_WEIGHT_0 WEIGHT_0
ENUM_STATIC_WEIGHT_1 WEIGHT_0
ENUM_STATIC_WEIGHT_2 WEIGHT_0
ENUM_STATIC_WEIGHT_3 WEIGHT_0
ENUM_STATIC_WEIGHT_4 WEIGHT_0
ENUM_STATIC_WEIGHT_5 WEIGHT_0
ENUM_SYNC_MODE_0 ASYNCHRONOUS
ENUM_SYNC_MODE_1 ASYNCHRONOUS
ENUM_SYNC_MODE_2 ASYNCHRONOUS
ENUM_SYNC_MODE_3 ASYNCHRONOUS
ENUM_SYNC_MODE_4 ASYNCHRONOUS
ENUM_SYNC_MODE_5 ASYNCHRONOUS
ENUM_TEST_MODE NORMAL_MODE
ENUM_THLD_JAR1_0 THRESHOLD_32
ENUM_THLD_JAR1_1 THRESHOLD_32
ENUM_THLD_JAR1_2 THRESHOLD_32
ENUM_THLD_JAR1_3 THRESHOLD_32
ENUM_THLD_JAR1_4 THRESHOLD_32
ENUM_THLD_JAR1_5 THRESHOLD_32
ENUM_THLD_JAR2_0 THRESHOLD_16
ENUM_THLD_JAR2_1 THRESHOLD_16
ENUM_THLD_JAR2_2 THRESHOLD_16
ENUM_THLD_JAR2_3 THRESHOLD_16
ENUM_THLD_JAR2_4 THRESHOLD_16
ENUM_THLD_JAR2_5 THRESHOLD_16
ENUM_USE_ALMOST_EMPTY_0 EMPTY
ENUM_USE_ALMOST_EMPTY_1 EMPTY
ENUM_USE_ALMOST_EMPTY_2 EMPTY
ENUM_USE_ALMOST_EMPTY_3 EMPTY
ENUM_USER_ECC_EN DISABLE
ENUM_USER_PRIORITY_0 PRIORITY_0
ENUM_USER_PRIORITY_1 PRIORITY_0
ENUM_USER_PRIORITY_2 PRIORITY_0
ENUM_USER_PRIORITY_3 PRIORITY_0
ENUM_USER_PRIORITY_4 PRIORITY_0
ENUM_USER_PRIORITY_5 PRIORITY_0
ENUM_WFIFO0_CPORT_MAP CMD_PORT_0
ENUM_WFIFO0_RDY_ALMOST_FULL NOT_FULL
ENUM_WFIFO1_CPORT_MAP CMD_PORT_0
ENUM_WFIFO1_RDY_ALMOST_FULL NOT_FULL
ENUM_WFIFO2_CPORT_MAP CMD_PORT_0
ENUM_WFIFO2_RDY_ALMOST_FULL NOT_FULL
ENUM_WFIFO3_CPORT_MAP CMD_PORT_0
ENUM_WFIFO3_RDY_ALMOST_FULL NOT_FULL
ENUM_WR_DWIDTH_0 DWIDTH_0
ENUM_WR_DWIDTH_1 DWIDTH_0
ENUM_WR_DWIDTH_2 DWIDTH_0
ENUM_WR_DWIDTH_3 DWIDTH_0
ENUM_WR_DWIDTH_4 DWIDTH_0
ENUM_WR_DWIDTH_5 DWIDTH_0
ENUM_WR_FIFO_IN_USE_0 FALSE
ENUM_WR_FIFO_IN_USE_1 FALSE
ENUM_WR_FIFO_IN_USE_2 FALSE
ENUM_WR_FIFO_IN_USE_3 FALSE
ENUM_WR_PORT_INFO_0 USE_NO
ENUM_WR_PORT_INFO_1 USE_NO
ENUM_WR_PORT_INFO_2 USE_NO
ENUM_WR_PORT_INFO_3 USE_NO
ENUM_WR_PORT_INFO_4 USE_NO
ENUM_WR_PORT_INFO_5 USE_NO
ENUM_WRITE_ODT_CHIP ODT_DISABLED
INTG_MEM_AUTO_PD_CYCLES 0
INTG_CYC_TO_RLD_JARS_0 1
INTG_CYC_TO_RLD_JARS_1 1
INTG_CYC_TO_RLD_JARS_2 1
INTG_CYC_TO_RLD_JARS_3 1
INTG_CYC_TO_RLD_JARS_4 1
INTG_CYC_TO_RLD_JARS_5 1
INTG_EXTRA_CTL_CLK_ACT_TO_ACT 0
INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK 0
INTG_EXTRA_CTL_CLK_ACT_TO_PCH 0
INTG_EXTRA_CTL_CLK_ACT_TO_RDWR 0
INTG_EXTRA_CTL_CLK_ARF_PERIOD 0
INTG_EXTRA_CTL_CLK_ARF_TO_VALID 0
INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT 0
INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID 0
INTG_EXTRA_CTL_CLK_PCH_TO_VALID 0
INTG_EXTRA_CTL_CLK_PDN_PERIOD 0
INTG_EXTRA_CTL_CLK_PDN_TO_VALID 0
INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID 0
INTG_EXTRA_CTL_CLK_RD_TO_PCH 0
INTG_EXTRA_CTL_CLK_RD_TO_RD 0
INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP 0
INTG_EXTRA_CTL_CLK_RD_TO_WR 0
INTG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
INTG_EXTRA_CTL_CLK_SRF_TO_VALID 0
INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL 0
INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID 0
INTG_EXTRA_CTL_CLK_WR_TO_PCH 0
INTG_EXTRA_CTL_CLK_WR_TO_RD 0
INTG_EXTRA_CTL_CLK_WR_TO_RD_BC 0
INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP 0
INTG_EXTRA_CTL_CLK_WR_TO_WR 0
INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP 0
INTG_MEM_IF_TREFI 3120
INTG_MEM_IF_TRFC 34
INTG_RCFG_SUM_WT_PRIORITY_0 0
INTG_RCFG_SUM_WT_PRIORITY_1 0
INTG_RCFG_SUM_WT_PRIORITY_2 0
INTG_RCFG_SUM_WT_PRIORITY_3 0
INTG_RCFG_SUM_WT_PRIORITY_4 0
INTG_RCFG_SUM_WT_PRIORITY_5 0
INTG_RCFG_SUM_WT_PRIORITY_6 0
INTG_RCFG_SUM_WT_PRIORITY_7 0
INTG_SUM_WT_PRIORITY_0 0
INTG_SUM_WT_PRIORITY_1 0
INTG_SUM_WT_PRIORITY_2 0
INTG_SUM_WT_PRIORITY_3 0
INTG_SUM_WT_PRIORITY_4 0
INTG_SUM_WT_PRIORITY_5 0
INTG_SUM_WT_PRIORITY_6 0
INTG_SUM_WT_PRIORITY_7 0
VECT_ATTR_COUNTER_ONE_MASK 0
VECT_ATTR_COUNTER_ONE_MATCH 0
VECT_ATTR_COUNTER_ZERO_MASK 0
VECT_ATTR_COUNTER_ZERO_MATCH 0
VECT_ATTR_DEBUG_SELECT_BYTE 0
INTG_POWER_SAVING_EXIT_CYCLES 5
INTG_MEM_CLK_ENTRY_CYCLES 10
ENUM_ENABLE_BURST_INTERRUPT DISABLED
ENUM_ENABLE_BURST_TERMINATE DISABLED
AV_PORT_0_CONNECT_TO_CV_PORT 0
CV_PORT_0_CONNECT_TO_AV_PORT 0
CV_AVL_DATA_WIDTH_PORT_0 0
CV_AVL_ADDR_WIDTH_PORT_0 0
CV_CPORT_TYPE_PORT_0 0
CV_AVL_NUM_SYMBOLS_PORT_0 2
CV_LSB_WFIFO_PORT_0 5
CV_MSB_WFIFO_PORT_0 5
CV_LSB_RFIFO_PORT_0 5
CV_MSB_RFIFO_PORT_0 5
CV_ENUM_AUTO_PCH_ENABLE_0 DISABLED
CV_ENUM_CMD_PORT_IN_USE_0 FALSE
CV_ENUM_CPORT0_RFIFO_MAP FIFO_0
CV_ENUM_CPORT0_TYPE DISABLE
CV_ENUM_CPORT0_WFIFO_MAP FIFO_0
CV_ENUM_ENABLE_BONDING_0 DISABLED
CV_ENUM_PORT0_WIDTH PORT_64_BIT
CV_ENUM_PRIORITY_0_0 WEIGHT_0
CV_ENUM_PRIORITY_1_0 WEIGHT_0
CV_ENUM_PRIORITY_2_0 WEIGHT_0
CV_ENUM_PRIORITY_3_0 WEIGHT_0
CV_ENUM_PRIORITY_4_0 WEIGHT_0
CV_ENUM_PRIORITY_5_0 WEIGHT_0
CV_ENUM_PRIORITY_6_0 WEIGHT_0
CV_ENUM_PRIORITY_7_0 WEIGHT_0
CV_ENUM_RCFG_STATIC_WEIGHT_0 WEIGHT_0
CV_ENUM_RCFG_USER_PRIORITY_0 PRIORITY_0
CV_ENUM_RD_DWIDTH_0 DWIDTH_0
CV_ENUM_RD_PORT_INFO_0 USE_NO
CV_ENUM_STATIC_WEIGHT_0 WEIGHT_0
CV_ENUM_USER_PRIORITY_0 PRIORITY_0
CV_ENUM_WR_DWIDTH_0 DWIDTH_0
CV_ENUM_WR_PORT_INFO_0 USE_NO
TG_TEMP_PORT_0 0
AV_PORT_1_CONNECT_TO_CV_PORT 1
CV_PORT_1_CONNECT_TO_AV_PORT 1
CV_AVL_DATA_WIDTH_PORT_1 0
CV_AVL_ADDR_WIDTH_PORT_1 0
CV_CPORT_TYPE_PORT_1 0
CV_AVL_NUM_SYMBOLS_PORT_1 2
CV_LSB_WFIFO_PORT_1 5
CV_MSB_WFIFO_PORT_1 5
CV_LSB_RFIFO_PORT_1 5
CV_MSB_RFIFO_PORT_1 5
CV_ENUM_AUTO_PCH_ENABLE_1 DISABLED
CV_ENUM_CMD_PORT_IN_USE_1 FALSE
CV_ENUM_CPORT1_RFIFO_MAP FIFO_0
CV_ENUM_CPORT1_TYPE DISABLE
CV_ENUM_CPORT1_WFIFO_MAP FIFO_0
CV_ENUM_ENABLE_BONDING_1 DISABLED
CV_ENUM_PORT1_WIDTH PORT_64_BIT
CV_ENUM_PRIORITY_0_1 WEIGHT_0
CV_ENUM_PRIORITY_1_1 WEIGHT_0
CV_ENUM_PRIORITY_2_1 WEIGHT_0
CV_ENUM_PRIORITY_3_1 WEIGHT_0
CV_ENUM_PRIORITY_4_1 WEIGHT_0
CV_ENUM_PRIORITY_5_1 WEIGHT_0
CV_ENUM_PRIORITY_6_1 WEIGHT_0
CV_ENUM_PRIORITY_7_1 WEIGHT_0
CV_ENUM_RCFG_STATIC_WEIGHT_1 WEIGHT_0
CV_ENUM_RCFG_USER_PRIORITY_1 PRIORITY_0
CV_ENUM_RD_DWIDTH_1 DWIDTH_0
CV_ENUM_RD_PORT_INFO_1 USE_NO
CV_ENUM_STATIC_WEIGHT_1 WEIGHT_0
CV_ENUM_USER_PRIORITY_1 PRIORITY_0
CV_ENUM_WR_DWIDTH_1 DWIDTH_0
CV_ENUM_WR_PORT_INFO_1 USE_NO
TG_TEMP_PORT_1 0
AV_PORT_2_CONNECT_TO_CV_PORT 2
CV_PORT_2_CONNECT_TO_AV_PORT 2
CV_AVL_DATA_WIDTH_PORT_2 0
CV_AVL_ADDR_WIDTH_PORT_2 0
CV_CPORT_TYPE_PORT_2 0
CV_AVL_NUM_SYMBOLS_PORT_2 2
CV_LSB_WFIFO_PORT_2 5
CV_MSB_WFIFO_PORT_2 5
CV_LSB_RFIFO_PORT_2 5
CV_MSB_RFIFO_PORT_2 5
CV_ENUM_AUTO_PCH_ENABLE_2 DISABLED
CV_ENUM_CMD_PORT_IN_USE_2 FALSE
CV_ENUM_CPORT2_RFIFO_MAP FIFO_0
CV_ENUM_CPORT2_TYPE DISABLE
CV_ENUM_CPORT2_WFIFO_MAP FIFO_0
CV_ENUM_ENABLE_BONDING_2 DISABLED
CV_ENUM_PORT2_WIDTH PORT_64_BIT
CV_ENUM_PRIORITY_0_2 WEIGHT_0
CV_ENUM_PRIORITY_1_2 WEIGHT_0
CV_ENUM_PRIORITY_2_2 WEIGHT_0
CV_ENUM_PRIORITY_3_2 WEIGHT_0
CV_ENUM_PRIORITY_4_2 WEIGHT_0
CV_ENUM_PRIORITY_5_2 WEIGHT_0
CV_ENUM_PRIORITY_6_2 WEIGHT_0
CV_ENUM_PRIORITY_7_2 WEIGHT_0
CV_ENUM_RCFG_STATIC_WEIGHT_2 WEIGHT_0
CV_ENUM_RCFG_USER_PRIORITY_2 PRIORITY_0
CV_ENUM_RD_DWIDTH_2 DWIDTH_0
CV_ENUM_RD_PORT_INFO_2 USE_NO
CV_ENUM_STATIC_WEIGHT_2 WEIGHT_0
CV_ENUM_USER_PRIORITY_2 PRIORITY_0
CV_ENUM_WR_DWIDTH_2 DWIDTH_0
CV_ENUM_WR_PORT_INFO_2 USE_NO
TG_TEMP_PORT_2 0
AV_PORT_3_CONNECT_TO_CV_PORT 3
CV_PORT_3_CONNECT_TO_AV_PORT 3
CV_AVL_DATA_WIDTH_PORT_3 0
CV_AVL_ADDR_WIDTH_PORT_3 0
CV_CPORT_TYPE_PORT_3 0
CV_AVL_NUM_SYMBOLS_PORT_3 2
CV_LSB_WFIFO_PORT_3 5
CV_MSB_WFIFO_PORT_3 5
CV_LSB_RFIFO_PORT_3 5
CV_MSB_RFIFO_PORT_3 5
CV_ENUM_AUTO_PCH_ENABLE_3 DISABLED
CV_ENUM_CMD_PORT_IN_USE_3 FALSE
CV_ENUM_CPORT3_RFIFO_MAP FIFO_0
CV_ENUM_CPORT3_TYPE DISABLE
CV_ENUM_CPORT3_WFIFO_MAP FIFO_0
CV_ENUM_ENABLE_BONDING_3 DISABLED
CV_ENUM_PORT3_WIDTH PORT_64_BIT
CV_ENUM_PRIORITY_0_3 WEIGHT_0
CV_ENUM_PRIORITY_1_3 WEIGHT_0
CV_ENUM_PRIORITY_2_3 WEIGHT_0
CV_ENUM_PRIORITY_3_3 WEIGHT_0
CV_ENUM_PRIORITY_4_3 WEIGHT_0
CV_ENUM_PRIORITY_5_3 WEIGHT_0
CV_ENUM_PRIORITY_6_3 WEIGHT_0
CV_ENUM_PRIORITY_7_3 WEIGHT_0
CV_ENUM_RCFG_STATIC_WEIGHT_3 WEIGHT_0
CV_ENUM_RCFG_USER_PRIORITY_3 PRIORITY_0
CV_ENUM_RD_DWIDTH_3 DWIDTH_0
CV_ENUM_RD_PORT_INFO_3 USE_NO
CV_ENUM_STATIC_WEIGHT_3 WEIGHT_0
CV_ENUM_USER_PRIORITY_3 PRIORITY_0
CV_ENUM_WR_DWIDTH_3 DWIDTH_0
CV_ENUM_WR_PORT_INFO_3 USE_NO
TG_TEMP_PORT_3 0
AV_PORT_4_CONNECT_TO_CV_PORT 4
CV_PORT_4_CONNECT_TO_AV_PORT 4
CV_AVL_DATA_WIDTH_PORT_4 0
CV_AVL_ADDR_WIDTH_PORT_4 0
CV_CPORT_TYPE_PORT_4 0
CV_AVL_NUM_SYMBOLS_PORT_4 2
CV_LSB_WFIFO_PORT_4 5
CV_MSB_WFIFO_PORT_4 5
CV_LSB_RFIFO_PORT_4 5
CV_MSB_RFIFO_PORT_4 5
CV_ENUM_AUTO_PCH_ENABLE_4 DISABLED
CV_ENUM_CMD_PORT_IN_USE_4 FALSE
CV_ENUM_CPORT4_RFIFO_MAP FIFO_0
CV_ENUM_CPORT4_TYPE DISABLE
CV_ENUM_CPORT4_WFIFO_MAP FIFO_0
CV_ENUM_ENABLE_BONDING_4 DISABLED
CV_ENUM_PORT4_WIDTH PORT_64_BIT
CV_ENUM_PRIORITY_0_4 WEIGHT_0
CV_ENUM_PRIORITY_1_4 WEIGHT_0
CV_ENUM_PRIORITY_2_4 WEIGHT_0
CV_ENUM_PRIORITY_3_4 WEIGHT_0
CV_ENUM_PRIORITY_4_4 WEIGHT_0
CV_ENUM_PRIORITY_5_4 WEIGHT_0
CV_ENUM_PRIORITY_6_4 WEIGHT_0
CV_ENUM_PRIORITY_7_4 WEIGHT_0
CV_ENUM_RCFG_STATIC_WEIGHT_4 WEIGHT_0
CV_ENUM_RCFG_USER_PRIORITY_4 PRIORITY_0
CV_ENUM_RD_DWIDTH_4 DWIDTH_0
CV_ENUM_RD_PORT_INFO_4 USE_NO
CV_ENUM_STATIC_WEIGHT_4 WEIGHT_0
CV_ENUM_USER_PRIORITY_4 PRIORITY_0
CV_ENUM_WR_DWIDTH_4 DWIDTH_0
CV_ENUM_WR_PORT_INFO_4 USE_NO
TG_TEMP_PORT_4 0
AV_PORT_5_CONNECT_TO_CV_PORT 5
CV_PORT_5_CONNECT_TO_AV_PORT 5
CV_AVL_DATA_WIDTH_PORT_5 0
CV_AVL_ADDR_WIDTH_PORT_5 0
CV_CPORT_TYPE_PORT_5 0
CV_AVL_NUM_SYMBOLS_PORT_5 2
CV_LSB_WFIFO_PORT_5 5
CV_MSB_WFIFO_PORT_5 5
CV_LSB_RFIFO_PORT_5 5
CV_MSB_RFIFO_PORT_5 5
CV_ENUM_AUTO_PCH_ENABLE_5 DISABLED
CV_ENUM_CMD_PORT_IN_USE_5 FALSE
CV_ENUM_CPORT5_RFIFO_MAP FIFO_0
CV_ENUM_CPORT5_TYPE DISABLE
CV_ENUM_CPORT5_WFIFO_MAP FIFO_0
CV_ENUM_ENABLE_BONDING_5 DISABLED
CV_ENUM_PORT5_WIDTH PORT_64_BIT
CV_ENUM_PRIORITY_0_5 WEIGHT_0
CV_ENUM_PRIORITY_1_5 WEIGHT_0
CV_ENUM_PRIORITY_2_5 WEIGHT_0
CV_ENUM_PRIORITY_3_5 WEIGHT_0
CV_ENUM_PRIORITY_4_5 WEIGHT_0
CV_ENUM_PRIORITY_5_5 WEIGHT_0
CV_ENUM_PRIORITY_6_5 WEIGHT_0
CV_ENUM_PRIORITY_7_5 WEIGHT_0
CV_ENUM_RCFG_STATIC_WEIGHT_5 WEIGHT_0
CV_ENUM_RCFG_USER_PRIORITY_5 PRIORITY_0
CV_ENUM_RD_DWIDTH_5 DWIDTH_0
CV_ENUM_RD_PORT_INFO_5 USE_NO
CV_ENUM_STATIC_WEIGHT_5 WEIGHT_0
CV_ENUM_USER_PRIORITY_5 PRIORITY_0
CV_ENUM_WR_DWIDTH_5 DWIDTH_0
CV_ENUM_WR_PORT_INFO_5 USE_NO
TG_TEMP_PORT_5 0
CV_ENUM_RFIFO0_CPORT_MAP CMD_PORT_0
CV_ENUM_WFIFO0_CPORT_MAP CMD_PORT_0
CV_ENUM_RFIFO1_CPORT_MAP CMD_PORT_0
CV_ENUM_WFIFO1_CPORT_MAP CMD_PORT_0
CV_ENUM_RFIFO2_CPORT_MAP CMD_PORT_0
CV_ENUM_WFIFO2_CPORT_MAP CMD_PORT_0
CV_ENUM_RFIFO3_CPORT_MAP CMD_PORT_0
CV_ENUM_WFIFO3_CPORT_MAP CMD_PORT_0
CV_INTG_RCFG_SUM_WT_PRIORITY_0 0
CV_INTG_SUM_WT_PRIORITY_0 0
CV_INTG_RCFG_SUM_WT_PRIORITY_1 0
CV_INTG_SUM_WT_PRIORITY_1 0
CV_INTG_RCFG_SUM_WT_PRIORITY_2 0
CV_INTG_SUM_WT_PRIORITY_2 0
CV_INTG_RCFG_SUM_WT_PRIORITY_3 0
CV_INTG_SUM_WT_PRIORITY_3 0
CV_INTG_RCFG_SUM_WT_PRIORITY_4 0
CV_INTG_SUM_WT_PRIORITY_4 0
CV_INTG_RCFG_SUM_WT_PRIORITY_5 0
CV_INTG_SUM_WT_PRIORITY_5 0
CV_INTG_RCFG_SUM_WT_PRIORITY_6 0
CV_INTG_SUM_WT_PRIORITY_6 0
CV_INTG_RCFG_SUM_WT_PRIORITY_7 0
CV_INTG_SUM_WT_PRIORITY_7 0
CONTINUE_AFTER_CAL_FAIL false
MAX10_CFG true
POWER_OF_TWO_BUS false
SOPC_COMPAT_RESET false
AVL_MAX_SIZE 4
BYTE_ENABLE true
ENABLE_CTRL_AVALON_INTERFACE true
CTL_DEEP_POWERDN_EN false
CTL_SELF_REFRESH_EN false
AUTO_POWERDN_EN false
AUTO_PD_CYCLES 0
CTL_USR_REFRESH_EN false
CTL_AUTOPCH_EN false
CTL_ZQCAL_EN false
ADDR_ORDER 0
CTL_LOOK_AHEAD_DEPTH 4
CONTROLLER_LATENCY 5
CFG_REORDER_DATA true
STARVE_LIMIT 10
CTL_CSR_ENABLED true
CTL_CSR_CONNECTION INTERNAL_JTAG
CTL_ECC_ENABLED true
CTL_HRB_ENABLED false
CTL_ECC_AUTO_CORRECTION_ENABLED false
MULTICAST_EN false
CTL_DYNAMIC_BANK_ALLOCATION false
CTL_DYNAMIC_BANK_NUM 4
DEBUG_MODE false
ENABLE_BURST_MERGE false
CTL_ENABLE_BURST_INTERRUPT false
CTL_ENABLE_BURST_TERMINATE false
LOCAL_ID_WIDTH 8
RDBUFFER_ADDR_WIDTH 7
WRBUFFER_ADDR_WIDTH 6
MAX_PENDING_WR_CMD 16
MAX_PENDING_RD_CMD 32
USE_MM_ADAPTOR true
USE_AXI_ADAPTOR false
HCX_COMPAT_MODE false
CTL_CMD_QUEUE_DEPTH 8
CTL_CSR_READ_ONLY 1
CFG_DATA_REORDERING_TYPE INTER_BANK
NUM_OF_PORTS 1
ENABLE_BONDING false
ENABLE_USER_ECC false
AVL_DATA_WIDTH_PORT 32,32,32,32,32,32
PRIORITY_PORT 1,1,1,1,1,1
WEIGHT_PORT 0,0,0,0,0,0
CPORT_TYPE_PORT Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional
CORE_PERIPHERY_DUAL_CLOCK false
USE_DR_CLK false
DLL_USE_DR_CLK false
USE_2X_FF false
DUAL_WRITE_CLOCK false
GENERIC_PLL false
USE_HARD_READ_FIFO false
READ_FIFO_HALF_RATE true
PLL_MASTER true
DLL_MASTER true
PHY_VERSION_NUMBER 150
ENABLE_NIOS_OCI false
ENABLE_EMIT_JTAG_MASTER false
ENABLE_NIOS_JTAG_UART false
ENABLE_NIOS_PRINTF_OUTPUT false
ENABLE_LARGE_RW_MGR_DI_BUFFER false
ENABLE_EMIT_BFM_MASTER false
FORCE_SEQUENCER_TCL_DEBUG_MODE false
ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT false
ENABLE_MAX_SIZE_SEQ_MEM false
MAKE_INTERNAL_NIOS_VISIBLE false
DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG false
ENABLE_CSR_SOFT_RESET_REQ false
DUPLICATE_PLL_FOR_PHY_CLK false
MAX_LATENCY_COUNT_WIDTH 5
READ_VALID_FIFO_SIZE 16
EXTRA_VFIFO_SHIFT 0
TB_MEM_CLK_FREQ 300.0
TB_RATE HALF
TB_MEM_IF_DQ_WIDTH 24
TB_MEM_IF_READ_DQS_WIDTH 3
TB_PLL_DLL_MASTER true
FAST_SIM_CALIBRATION false
REF_CLK_FREQ 50.0
REF_CLK_FREQ_STR 50.0 MHz
REF_CLK_NS 20.0
REF_CLK_PS 20000.0
PLL_DR_CLK_FREQ 0.0
PLL_DR_CLK_FREQ_STR
PLL_DR_CLK_FREQ_SIM_STR 0 ps
PLL_DR_CLK_PHASE_PS 0
PLL_DR_CLK_PHASE_PS_STR
PLL_DR_CLK_PHASE_DEG 0.0
PLL_DR_CLK_PHASE_PS_SIM 0
PLL_DR_CLK_PHASE_PS_SIM_STR
PLL_DR_CLK_PHASE_DEG_SIM 0.0
PLL_DR_CLK_MULT 0
PLL_DR_CLK_DIV 0
PLL_MEM_CLK_FREQ 300.0
PLL_MEM_CLK_FREQ_STR 300.0 MHz
PLL_MEM_CLK_FREQ_SIM_STR 3334 ps
PLL_MEM_CLK_PHASE_PS 0
PLL_MEM_CLK_PHASE_PS_STR 0 ps
PLL_MEM_CLK_PHASE_DEG 0.0
PLL_MEM_CLK_PHASE_PS_SIM 0
PLL_MEM_CLK_PHASE_PS_SIM_STR 0 ps
PLL_MEM_CLK_PHASE_DEG_SIM 0.0
PLL_MEM_CLK_MULT 6
PLL_MEM_CLK_DIV 1
PLL_AFI_CLK_FREQ 150.0
PLL_AFI_CLK_FREQ_STR 150.0 MHz
PLL_AFI_CLK_FREQ_SIM_STR 6668 ps
PLL_AFI_CLK_PHASE_PS 0
PLL_AFI_CLK_PHASE_PS_STR 0 ps
PLL_AFI_CLK_PHASE_DEG 0.0
PLL_AFI_CLK_PHASE_PS_SIM 0
PLL_AFI_CLK_PHASE_PS_SIM_STR 0 ps
PLL_AFI_CLK_PHASE_DEG_SIM 0.0
PLL_AFI_CLK_MULT 3
PLL_AFI_CLK_DIV 1
PLL_WRITE_CLK_FREQ 300.0
PLL_WRITE_CLK_FREQ_STR 300.0 MHz
PLL_WRITE_CLK_FREQ_SIM_STR 3334 ps
PLL_WRITE_CLK_PHASE_PS 2500
PLL_WRITE_CLK_PHASE_PS_STR 2500 ps
PLL_WRITE_CLK_PHASE_DEG 270.0
PLL_WRITE_CLK_PHASE_PS_SIM 2500
PLL_WRITE_CLK_PHASE_PS_SIM_STR 2500 ps
PLL_WRITE_CLK_PHASE_DEG_SIM 270.0
PLL_WRITE_CLK_MULT 6
PLL_WRITE_CLK_DIV 1
PLL_ADDR_CMD_CLK_FREQ 300.0
PLL_ADDR_CMD_CLK_FREQ_STR 300.0 MHz
PLL_ADDR_CMD_CLK_FREQ_SIM_STR 3334 ps
PLL_ADDR_CMD_CLK_PHASE_PS 0
PLL_ADDR_CMD_CLK_PHASE_PS_STR 0 ps
PLL_ADDR_CMD_CLK_PHASE_DEG 0.0
PLL_ADDR_CMD_CLK_PHASE_PS_SIM 0
PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR 0 ps
PLL_ADDR_CMD_CLK_PHASE_DEG_SIM 0.0
PLL_ADDR_CMD_CLK_MULT 6
PLL_ADDR_CMD_CLK_DIV 1
PLL_AFI_HALF_CLK_FREQ 300.0
PLL_AFI_HALF_CLK_FREQ_STR 300.0 MHz
PLL_AFI_HALF_CLK_FREQ_SIM_STR 3334 ps
PLL_AFI_HALF_CLK_PHASE_PS 2500
PLL_AFI_HALF_CLK_PHASE_PS_STR 2500 ps
PLL_AFI_HALF_CLK_PHASE_DEG 270.0
PLL_AFI_HALF_CLK_PHASE_PS_SIM 2500
PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR 2500 ps
PLL_AFI_HALF_CLK_PHASE_DEG_SIM 270.0
PLL_AFI_HALF_CLK_MULT 6
PLL_AFI_HALF_CLK_DIV 1
PLL_NIOS_CLK_FREQ 0.0
PLL_NIOS_CLK_FREQ_STR
PLL_NIOS_CLK_FREQ_SIM_STR 0 ps
PLL_NIOS_CLK_PHASE_PS 0
PLL_NIOS_CLK_PHASE_PS_STR
PLL_NIOS_CLK_PHASE_DEG 0.0
PLL_NIOS_CLK_PHASE_PS_SIM 0
PLL_NIOS_CLK_PHASE_PS_SIM_STR
PLL_NIOS_CLK_PHASE_DEG_SIM 0.0
PLL_NIOS_CLK_MULT 0
PLL_NIOS_CLK_DIV 0
PLL_CONFIG_CLK_FREQ 0.0
PLL_CONFIG_CLK_FREQ_STR
PLL_CONFIG_CLK_FREQ_SIM_STR 0 ps
PLL_CONFIG_CLK_PHASE_PS 0
PLL_CONFIG_CLK_PHASE_PS_STR
PLL_CONFIG_CLK_PHASE_DEG 0.0
PLL_CONFIG_CLK_PHASE_PS_SIM 0
PLL_CONFIG_CLK_PHASE_PS_SIM_STR
PLL_CONFIG_CLK_PHASE_DEG_SIM 0.0
PLL_CONFIG_CLK_MULT 0
PLL_CONFIG_CLK_DIV 0
PLL_P2C_READ_CLK_FREQ 0.0
PLL_P2C_READ_CLK_FREQ_STR
PLL_P2C_READ_CLK_FREQ_SIM_STR 0 ps
PLL_P2C_READ_CLK_PHASE_PS 0
PLL_P2C_READ_CLK_PHASE_PS_STR
PLL_P2C_READ_CLK_PHASE_DEG 0.0
PLL_P2C_READ_CLK_PHASE_PS_SIM 0
PLL_P2C_READ_CLK_PHASE_PS_SIM_STR
PLL_P2C_READ_CLK_PHASE_DEG_SIM 0.0
PLL_P2C_READ_CLK_MULT 0
PLL_P2C_READ_CLK_DIV 0
PLL_C2P_WRITE_CLK_FREQ 0.0
PLL_C2P_WRITE_CLK_FREQ_STR
PLL_C2P_WRITE_CLK_FREQ_SIM_STR 0 ps
PLL_C2P_WRITE_CLK_PHASE_PS 0
PLL_C2P_WRITE_CLK_PHASE_PS_STR
PLL_C2P_WRITE_CLK_PHASE_DEG 0.0
PLL_C2P_WRITE_CLK_PHASE_PS_SIM 0
PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR
PLL_C2P_WRITE_CLK_PHASE_DEG_SIM 0.0
PLL_C2P_WRITE_CLK_MULT 0
PLL_C2P_WRITE_CLK_DIV 0
PLL_HR_CLK_FREQ 0.0
PLL_HR_CLK_FREQ_STR
PLL_HR_CLK_FREQ_SIM_STR 0 ps
PLL_HR_CLK_PHASE_PS 0
PLL_HR_CLK_PHASE_PS_STR
PLL_HR_CLK_PHASE_DEG 0.0
PLL_HR_CLK_PHASE_PS_SIM 0
PLL_HR_CLK_PHASE_PS_SIM_STR
PLL_HR_CLK_PHASE_DEG_SIM 0.0
PLL_HR_CLK_MULT 0
PLL_HR_CLK_DIV 0
PLL_AFI_PHY_CLK_FREQ 0.0
PLL_AFI_PHY_CLK_FREQ_STR
PLL_AFI_PHY_CLK_FREQ_SIM_STR 0 ps
PLL_AFI_PHY_CLK_PHASE_PS 0
PLL_AFI_PHY_CLK_PHASE_PS_STR
PLL_AFI_PHY_CLK_PHASE_DEG 0.0
PLL_AFI_PHY_CLK_PHASE_PS_SIM 0
PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR
PLL_AFI_PHY_CLK_PHASE_DEG_SIM 0.0
PLL_AFI_PHY_CLK_MULT 0
PLL_AFI_PHY_CLK_DIV 0
REF_CLK_FREQ_CACHE_VALID true
REF_CLK_FREQ_PARAM_VALID false
REF_CLK_FREQ_MIN_PARAM 0.0
REF_CLK_FREQ_MAX_PARAM 0.0
REF_CLK_FREQ_MIN_CACHE 10.0
REF_CLK_FREQ_MAX_CACHE 500.0
PLL_DR_CLK_FREQ_PARAM 0.0
PLL_DR_CLK_FREQ_SIM_STR_PARAM
PLL_DR_CLK_PHASE_PS_PARAM 0
PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM
PLL_DR_CLK_MULT_PARAM 0
PLL_DR_CLK_DIV_PARAM 0
PLL_DR_CLK_FREQ_CACHE 0.0
PLL_DR_CLK_FREQ_SIM_STR_CACHE
PLL_DR_CLK_PHASE_PS_CACHE 0
PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE
PLL_DR_CLK_MULT_CACHE 0
PLL_DR_CLK_DIV_CACHE 0
PLL_MEM_CLK_FREQ_PARAM 0.0
PLL_MEM_CLK_FREQ_SIM_STR_PARAM
PLL_MEM_CLK_PHASE_PS_PARAM 0
PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM
PLL_MEM_CLK_MULT_PARAM 0
PLL_MEM_CLK_DIV_PARAM 0
PLL_MEM_CLK_FREQ_CACHE 300.0
PLL_MEM_CLK_FREQ_SIM_STR_CACHE 3334 ps
PLL_MEM_CLK_PHASE_PS_CACHE 0
PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE 0 ps
PLL_MEM_CLK_MULT_CACHE 6
PLL_MEM_CLK_DIV_CACHE 1
PLL_AFI_CLK_FREQ_PARAM 0.0
PLL_AFI_CLK_FREQ_SIM_STR_PARAM
PLL_AFI_CLK_PHASE_PS_PARAM 0
PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM
PLL_AFI_CLK_MULT_PARAM 0
PLL_AFI_CLK_DIV_PARAM 0
PLL_AFI_CLK_FREQ_CACHE 150.0
PLL_AFI_CLK_FREQ_SIM_STR_CACHE 6668 ps
PLL_AFI_CLK_PHASE_PS_CACHE 0
PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE 0 ps
PLL_AFI_CLK_MULT_CACHE 3
PLL_AFI_CLK_DIV_CACHE 1
PLL_WRITE_CLK_FREQ_PARAM 0.0
PLL_WRITE_CLK_FREQ_SIM_STR_PARAM
PLL_WRITE_CLK_PHASE_PS_PARAM 0
PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM
PLL_WRITE_CLK_MULT_PARAM 0
PLL_WRITE_CLK_DIV_PARAM 0
PLL_WRITE_CLK_FREQ_CACHE 300.0
PLL_WRITE_CLK_FREQ_SIM_STR_CACHE 3334 ps
PLL_WRITE_CLK_PHASE_PS_CACHE 2500
PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE 2500 ps
PLL_WRITE_CLK_MULT_CACHE 6
PLL_WRITE_CLK_DIV_CACHE 1
PLL_ADDR_CMD_CLK_FREQ_PARAM 0.0
PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM
PLL_ADDR_CMD_CLK_PHASE_PS_PARAM 0
PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM
PLL_ADDR_CMD_CLK_MULT_PARAM 0
PLL_ADDR_CMD_CLK_DIV_PARAM 0
PLL_ADDR_CMD_CLK_FREQ_CACHE 300.0
PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE 3334 ps
PLL_ADDR_CMD_CLK_PHASE_PS_CACHE 0
PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE 0 ps
PLL_ADDR_CMD_CLK_MULT_CACHE 6
PLL_ADDR_CMD_CLK_DIV_CACHE 1
PLL_AFI_HALF_CLK_FREQ_PARAM 0.0
PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM
PLL_AFI_HALF_CLK_PHASE_PS_PARAM 0
PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM
PLL_AFI_HALF_CLK_MULT_PARAM 0
PLL_AFI_HALF_CLK_DIV_PARAM 0
PLL_AFI_HALF_CLK_FREQ_CACHE 300.0
PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE 3334 ps
PLL_AFI_HALF_CLK_PHASE_PS_CACHE 2500
PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE 2500 ps
PLL_AFI_HALF_CLK_MULT_CACHE 6
PLL_AFI_HALF_CLK_DIV_CACHE 1
PLL_NIOS_CLK_FREQ_PARAM 0.0
PLL_NIOS_CLK_FREQ_SIM_STR_PARAM
PLL_NIOS_CLK_PHASE_PS_PARAM 0
PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM
PLL_NIOS_CLK_MULT_PARAM 0
PLL_NIOS_CLK_DIV_PARAM 0
PLL_NIOS_CLK_FREQ_CACHE 0.0
PLL_NIOS_CLK_FREQ_SIM_STR_CACHE
PLL_NIOS_CLK_PHASE_PS_CACHE 0
PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE
PLL_NIOS_CLK_MULT_CACHE 0
PLL_NIOS_CLK_DIV_CACHE 0
PLL_CONFIG_CLK_FREQ_PARAM 0.0
PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM
PLL_CONFIG_CLK_PHASE_PS_PARAM 0
PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM
PLL_CONFIG_CLK_MULT_PARAM 0
PLL_CONFIG_CLK_DIV_PARAM 0
PLL_CONFIG_CLK_FREQ_CACHE 0.0
PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE
PLL_CONFIG_CLK_PHASE_PS_CACHE 0
PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE
PLL_CONFIG_CLK_MULT_CACHE 0
PLL_CONFIG_CLK_DIV_CACHE 0
PLL_P2C_READ_CLK_FREQ_PARAM 0.0
PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM
PLL_P2C_READ_CLK_PHASE_PS_PARAM 0
PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM
PLL_P2C_READ_CLK_MULT_PARAM 0
PLL_P2C_READ_CLK_DIV_PARAM 0
PLL_P2C_READ_CLK_FREQ_CACHE 0.0
PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE
PLL_P2C_READ_CLK_PHASE_PS_CACHE 0
PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE
PLL_P2C_READ_CLK_MULT_CACHE 0
PLL_P2C_READ_CLK_DIV_CACHE 0
PLL_C2P_WRITE_CLK_FREQ_PARAM 0.0
PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM
PLL_C2P_WRITE_CLK_PHASE_PS_PARAM 0
PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM
PLL_C2P_WRITE_CLK_MULT_PARAM 0
PLL_C2P_WRITE_CLK_DIV_PARAM 0
PLL_C2P_WRITE_CLK_FREQ_CACHE 0.0
PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE
PLL_C2P_WRITE_CLK_PHASE_PS_CACHE 0
PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE
PLL_C2P_WRITE_CLK_MULT_CACHE 0
PLL_C2P_WRITE_CLK_DIV_CACHE 0
PLL_HR_CLK_FREQ_PARAM 0.0
PLL_HR_CLK_FREQ_SIM_STR_PARAM
PLL_HR_CLK_PHASE_PS_PARAM 0
PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM
PLL_HR_CLK_MULT_PARAM 0
PLL_HR_CLK_DIV_PARAM 0
PLL_HR_CLK_FREQ_CACHE 0.0
PLL_HR_CLK_FREQ_SIM_STR_CACHE
PLL_HR_CLK_PHASE_PS_CACHE 0
PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE
PLL_HR_CLK_MULT_CACHE 0
PLL_HR_CLK_DIV_CACHE 0
PLL_AFI_PHY_CLK_FREQ_PARAM 0.0
PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM
PLL_AFI_PHY_CLK_PHASE_PS_PARAM 0
PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM
PLL_AFI_PHY_CLK_MULT_PARAM 0
PLL_AFI_PHY_CLK_DIV_PARAM 0
PLL_AFI_PHY_CLK_FREQ_CACHE 0.0
PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE
PLL_AFI_PHY_CLK_PHASE_PS_CACHE 0
PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE
PLL_AFI_PHY_CLK_MULT_CACHE 0
PLL_AFI_PHY_CLK_DIV_CACHE 0
SPEED_GRADE_CACHE 6
IS_ES_DEVICE_CACHE false
MEM_CLK_FREQ_CACHE 300.0
REF_CLK_FREQ_CACHE 50.0
RATE_CACHE Half
HCX_COMPAT_MODE_CACHE false
PARSE_FRIENDLY_DEVICE_FAMILY_CACHE MAX10
COMMAND_PHASE_CACHE 0.0
MEM_CK_PHASE_CACHE 0.0
P2C_READ_CLOCK_ADD_PHASE_CACHE 0.0
C2P_WRITE_CLOCK_ADD_PHASE_CACHE 0.0
ACV_PHY_CLK_ADD_FR_PHASE_CACHE 0.0
SEQUENCER_TYPE_CACHE NIOS
USE_MEM_CLK_FREQ_CACHE false
PLL_CLK_CACHE_VALID true
PLL_CLK_PARAM_VALID false
ENABLE_EXTRA_REPORTING false
NUM_EXTRA_REPORT_PATH 10
ENABLE_ISS_PROBES false
CALIB_REG_WIDTH 8
USE_SEQUENCER_BFM false
PLL_SHARING_MODE None
NUM_PLL_SHARING_INTERFACES 1
EXPORT_AFI_HALF_CLK false
ABSTRACT_REAL_COMPARE_TEST false
INCLUDE_BOARD_DELAY_MODEL false
INCLUDE_MULTIRANK_BOARD_DELAY_MODEL false
USE_FAKE_PHY_INTERNAL false
USE_FAKE_PHY false
FORCE_MAX_LATENCY_COUNT_WIDTH 0
USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE false
ENABLE_NON_DESTRUCTIVE_CALIB false
USE_USER_RDIMM_VALUE false
ENABLE_DELAY_CHAIN_WRITE false
TRACKING_ERROR_TEST false
TRACKING_WATCH_TEST false
MARGIN_VARIATION_TEST false
AC_ROM_USER_ADD_0 0_0000_0000_0000
AC_ROM_USER_ADD_1 0_0000_0000_1000
TREFI 35100
REFRESH_INTERVAL 15000
ENABLE_NON_DES_CAL_TEST false
TRFC 350
ENABLE_NON_DES_CAL false
EXTRA_SETTINGS
MEM_DEVICE MISSING_MODEL
FORCE_SYNTHESIS_LANGUAGE
NUM_SUBGROUP_PER_READ_DQS 1
QVLD_EXTRA_FLOP_STAGES 0
QVLD_WR_ADDRESS_OFFSET 4
MAX_WRITE_LATENCY_COUNT_WIDTH 4
NUM_WRITE_PATH_FLOP_STAGES 1
NUM_AC_FR_CYCLE_SHIFTS 0
FORCED_NUM_WRITE_FR_CYCLE_SHIFTS 0
NUM_WRITE_FR_CYCLE_SHIFTS 1
PERFORM_READ_AFTER_WRITE_CALIBRATION false
SEQ_BURST_COUNT_WIDTH 1
VCALIB_COUNT_WIDTH 2
PLL_PHASE_COUNTER_WIDTH 4
DQS_DELAY_CHAIN_PHASE_SETTING 2
DQS_PHASE_SHIFT 9000
DELAYED_CLOCK_PHASE_SETTING 2
IO_DQS_IN_RESERVE 3
IO_DQS_OUT_RESERVE 3
IO_DQ_OUT_RESERVE 0
IO_DM_OUT_RESERVE 0
IO_DQS_EN_DELAY_OFFSET 0
IO_DQS_EN_PHASE_MAX 7
IO_DQDQS_OUT_PHASE_MAX 14
IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS false
MEM_CLK_NS 3.333
MEM_CLK_PS 3333.0
CALIB_LFIFO_OFFSET 4
CALIB_VFIFO_OFFSET 12
DELAY_PER_OPA_TAP 416
DELAY_PER_DCHAIN_TAP 50
DELAY_PER_DQS_EN_DCHAIN_TAP 50
DQS_EN_DELAY_MAX 7
DQS_IN_DELAY_MAX 15
IO_IN_DELAY_MAX 15
IO_OUT1_DELAY_MAX 15
IO_OUT2_DELAY_MAX 7
IO_STANDARD SSTL-15
VFIFO_AS_SHIFT_REG true
SEQUENCER_TYPE NIOS
NIOS_HEX_FILE_LOCATION ../
ADVERTIZE_SEQUENCER_SW_BUILD_FILES false
NEGATIVE_WRITE_CK_PHASE true
MEM_T_WL 5
MEM_T_RL 5
PHY_CLKBUF false
USE_LDC_AS_LOW_SKEW_CLOCK false
USE_LDC_FOR_ADDR_CMD false
ENABLE_LDC_MEM_CK_ADJUSTMENT false
MEM_CK_LDC_ADJUSTMENT_THRESHOLD 0
LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT true
LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE 0
FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT false
NON_LDC_ADDR_CMD_MEM_CK_INVERT false
REGISTER_C2P false
EARLY_ADDR_CMD_CLK_TRANSFER false
MAX10_RTL_SEQ true
PHY_ONLY false
SEQ_MODE 0
ADVANCED_CK_PHASES false
COMMAND_PHASE 0.0
MEM_CK_PHASE 0.0
P2C_READ_CLOCK_ADD_PHASE 0.0
C2P_WRITE_CLOCK_ADD_PHASE 0.0
ACV_PHY_CLK_ADD_FR_PHASE 0.0
MEM_VOLTAGE 1.5V DDR3
PLL_LOCATION Top_Bottom
SKIP_MEM_INIT true
READ_DQ_DQS_CLOCK_SOURCE INVERTED_DQS_BUS
DQ_INPUT_REG_USE_CLKN false
DQS_DQSN_MODE DIFFERENTIAL
AFI_DEBUG_INFO_WIDTH 32
CALIBRATION_MODE Skip
NIOS_ROM_DATA_WIDTH 32
NIOS_ROM_ADDRESS_WIDTH 13
READ_FIFO_SIZE 8
PHY_CSR_ENABLED false
PHY_CSR_CONNECTION INTERNAL_JTAG
USER_DEBUG_LEVEL 1
TIMING_BOARD_DERATE_METHOD AUTO
TIMING_BOARD_CK_CKN_SLEW_RATE 2.0
TIMING_BOARD_AC_SLEW_RATE 1.0
TIMING_BOARD_DQS_DQSN_SLEW_RATE 2.0
TIMING_BOARD_DQ_SLEW_RATE 1.0
TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED 2.0
TIMING_BOARD_AC_SLEW_RATE_APPLIED 1.0
TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED 2.0
TIMING_BOARD_DQ_SLEW_RATE_APPLIED 1.0
TIMING_BOARD_TIS 0.0
TIMING_BOARD_TIH 0.0
TIMING_BOARD_TDS 0.0
TIMING_BOARD_TDH 0.0
TIMING_BOARD_TIS_APPLIED 0.32
TIMING_BOARD_TIH_APPLIED 0.22
TIMING_BOARD_TDS_APPLIED 0.16
TIMING_BOARD_TDH_APPLIED 0.145
TIMING_BOARD_ISI_METHOD AUTO
TIMING_BOARD_AC_EYE_REDUCTION_SU 0.0
TIMING_BOARD_AC_EYE_REDUCTION_H 0.0
TIMING_BOARD_DQ_EYE_REDUCTION 0.0
TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME 0.0
TIMING_BOARD_READ_DQ_EYE_REDUCTION 0.0
TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME 0.0
TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED 0.0
TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED 0.0
TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED 0.0
TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED 0.0
TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED 0.0
TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED 0.0
PACKAGE_DESKEW false
AC_PACKAGE_DESKEW false
TIMING_BOARD_MAX_CK_DELAY 0.2443
TIMING_BOARD_MAX_DQS_DELAY 0.21929
TIMING_BOARD_SKEW_CKDQS_DIMM_MIN 0.02286
TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED 0.02286
TIMING_BOARD_SKEW_CKDQS_DIMM_MAX 0.04429
TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED 0.04429
TIMING_BOARD_SKEW_BETWEEN_DIMMS 0.05
TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED 0.0
TIMING_BOARD_SKEW_WITHIN_DQS 0.01806
TIMING_BOARD_SKEW_BETWEEN_DQS 0.04246
TIMING_BOARD_DQ_TO_DQS_SKEW -0.01152
TIMING_BOARD_AC_SKEW 0.07801
TIMING_BOARD_AC_TO_CK_SKEW -0.04709
ENABLE_EXPORT_SEQ_DEBUG_BRIDGE false
CORE_DEBUG_CONNECTION EXPORT
ADD_EXTERNAL_SEQ_DEBUG_NIOS false
ED_EXPORT_SEQ_DEBUG false
ADD_EFFICIENCY_MONITOR false
ENABLE_ABS_RAM_MEM_INIT false
ENABLE_ABS_RAM_INTERNAL false
ENABLE_ABSTRACT_RAM false
ABS_RAM_MEM_INIT_FILENAME meminit
DLL_DELAY_CTRL_WIDTH 6
DLL_OFFSET_CTRL_WIDTH 6
DELAY_BUFFER_MODE HIGH
DELAY_CHAIN_LENGTH 8
DLL_SHARING_MODE None
NUM_DLL_SHARING_INTERFACES 1
OCT_TERM_CONTROL_WIDTH 14
OCT_SHARING_MODE None
NUM_OCT_SHARING_INTERFACES 1
AUTO_DEVICE 10M50DAF484C6GES
AUTO_DEVICE_SPEEDGRADE 6
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

product_info_0

product_info v1.0
master_0 master   product_info_0
  avalon_slave_0
sys_clk clk  
  clock_reset
clk_reset  
  clock_reset_reset


Parameters

AUTO_DEVICE_FAMILY MAX10FPGA
AUTO_CLOCK_RESET_CLOCK_RATE 50000000
deviceFamily MAX 10
generateLegacySim false
  

Software Assignments

(none)

sys_clk

clock_source v15.0


Parameters

clockFrequency 50000000
clockFrequencyKnown true
inputClockFrequency 0
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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