Sigma Delta Converter Design Example v9.1 README File This readme file for the Unity Gain in Cascaded IFFT and FFT Pair Design contains information about the design example posted on the Altera Support website: http://www.altera.com/support/examples/exm-index.html Ensure that you have read the information on the design example web page before using the example. This readme file contains the following sections: o Package Contents o Tool Requirements o DSP Builder Simulation o Quartus II Compilation o Release History o Design Examples Disclaimer o Contacting Altera Package Contents ================ Sigma Delta Converter Design Example v9.1 Design files in the zip download include: o source.mdl - Simulink file to generate stimulus to design file dec2x2x2x2x2x2x.mdl o bit_stream.mat - Bit stream generated by source.mdl and provide as stimulus to decimation by 64 filter o dec64_filter_design.m - MATLAB script to generate filter coefficient o setup_dec2x2x2x2x2x2x_dspba.m - Setup script for DSP Builder design file dec2x2x2x2x2x2x.mdl o dec2x2x2x2x2x2x.mdl - DSP Builder design file Tool Requirements ================= This design example requires the following software package: o Quartus II 9.1 o DSP Builder Advanced Blockset 9.1 o MATLAB/Simulink version R2009a or later Please contact your local sales representative if you do not have one of these software tools. Description of Design Example ============================= This design example is a cost-effective, high-precision analog-to-digital converter (ADC) commonly used in wireless and audio applications, consisting of two major blocks: analog modulator and digital filter. The analog modulator over-samples and converts the analog signal into a stream of bits. The digital filter then converts the serial stream into digital number by decimation operation. This design example shows an efficient and cost-effective way to implement the digital decimation filter with multi-stage partition method and use the time-division multiplexed (TDM) feature in DSP Builder Advanced Blockset to achieve both high-speed performance and low-resource usage. DSP Builder Simulation ====================== To run the simulation of the data path in Simulink, perform the following steps: 1. In MATLAB, change the directory to the ..\sigma_delta_converter directory 2. Open the design file dec2x2x2x2x2x2x.mdl 3. Click "Start Simulation" icon 4. Compare the result from the OutScope with the Sine Wave source in source.mdl To get more details on the design flow using DSP Builder, refer to the DSP Builder User Guide located at: http://www.altera.com/literature/ug/ug_dsp_builder.pdf Quartus II Compilation ====================== To run the compilation for the Sigma Delta Converter project in Quartus II, perform the following steps: 1. In MATLAB, change the directory to the ..\sigma_delta_converter directory 2. Open the design file dec2x2x2x2x2x2x.mdl 3. Click "Run Quartus II" icon and launch Qaurtus II 9.1 4. You are ready to compile the design in Quartus II: Processing -> Start Compilation Release History =============== Version 9.1 January 2010 Initial release Design Examples Disclaimer ========================== These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is?basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera. Contacting Altera ================= Although we have made every effort to ensure that this design example works correctly, there might be problems that we have not encountered. If you have a question or problem that is not answered by the information provided in this readme file or the example's documentation, please contact your Altera Field Applications Engineer. If you have additional questions that are not answered in the documentation provided with this function, please contact Altera Applications: World-Wide Web: http://www.altera.com http://www.altera.com/mysupport/ Technical Support Hotline: (800) 800-EPLD (U.S.) (408) 544-7000 (Internationally) Copyright (c) 2010 Altera Corporation. All rights reserved.