Verilog Counter Design Example v1.0 README File This readme file for the Verilog Counter Design contains information about the design example in the Recommended HDL Coding Styles Chapter of Volume 1 of the Quartus II Handbook. Ensure that you have read the information on the Verilog Counter Design Example web page before using the example. This file contains the following information: o Package Contents o Software Tool Requirements o Release History o Contacting Altera Package Contents ================ Verilog Counter Design Example v1.0 Software Tool Requirements ========================== The Quartus II software version 4.0 or later, or the Mentor Graphics Precision RTL Synthesis 2003, or Synplicity Synplify Pro 7.3.3. Please contact your local sales representative if you do not have one of these tools. Release History ================ Version 1.0.0 ------------- - First release of example. Contacting Altera ================= Although we have made every effort to ensure that this design example works correctly, there might be problems that we have not encountered. If you have a question or problem that is not answered by the information provided in this readme file or the example's documentation, please contact your Altera Field Applications Engineer. If you have additional questions that are not answered in the documentation provided with this function, please contact Altera Applications: World-Wide Web: http://www.altera.com http://www.altera.com/mysupport/ Technical Support Hotline: (800) 800-EPLD (U.S.) (408) 544-7000 (Internationally) Copyright (c) 2004 Altera Corporation. All rights reserved.