Module Instance | Base Address | Register Address |
---|---|---|
i_io48_hmc_mmr_io48_mmr | 0xFFCFA000 | 0xFFCFA050 |
Offset: 0x50
Access: RW
Bit Fields | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
cfg_mem_clk_disable_entry_cycles 0x0 |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
cfg_mem_clk_disable_entry_cycles 0x0 |
cfg_power_saving_exit_cycles 0x0 |
cfg_tcl 0x0 |
Bit | Name | Description | Access | Reset |
---|---|---|---|---|
18:13 | cfg_mem_clk_disable_entry_cycles | Set to a the number of clocks after the execution of an self-refresh to stop the clock. This register is generally set based on PHY design latency and should generally not be changed. |
RW | 0x0 |
12:7 | cfg_power_saving_exit_cycles | The minimum number of cycles to stay in a low power state. This applies to both power down and self-refresh and should be set to the greater of tPD and tCKESR. |
RW | 0x0 |
6:0 | cfg_tcl | Memory read latency. |
RW | 0x0 |