Module Instance | Base Address | Register Address |
---|---|---|
i_io48_hmc_mmr_io48_mmr | 0xFFCFA000 | 0xFFCFA058 |
Offset: 0x58
Access: RW
Bit Fields | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
cfg_rd_odt_period 0x0 |
cfg_wr_odt_period 0x0 |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
cfg_wr_odt_period 0x0 |
cfg_rd_odt_on 0x0 |
cfg_wr_odt_on 0x0 |
Bit | Name | Description | Access | Reset |
---|---|---|---|---|
23:18 | cfg_rd_odt_period | Indicates number of memory clock cycle read ODT signal should stay asserted after rising edge |
RW | 0x0 |
17:12 | cfg_wr_odt_period | Indicates number of memory clock cycle write ODT signal should stay asserted after rising edge |
RW | 0x0 |
11:6 | cfg_rd_odt_on | Indicates number of memory clock cycle gap between read command and ODT signal rising edge |
RW | 0x0 |
5:0 | cfg_wr_odt_on | Indicates number of memory clock cycle gap between write command and ODT signal rising edge |
RW | 0x0 |