Registers used by the EMAC. All fields are reset by a cold or warm reset.
Module Instance | Base Address | Register Address |
---|---|---|
i_sys_mgr_core | 0xFFD06000 | 0xFFD06044 |
Offset: 0x44
Access: RW
Bit Fields | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
axi_disable RW 0x0 |
Reserved |
awprot RW 0x2 |
Reserved |
arprot RW 0x2 |
awcache RW 0x0 |
arcache RW 0x0 |
|||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
ptp_ref_sel RW 0x0 |
Reserved |
phy_intf_sel RW 0x3 |
Bit | Name | Description | Access | Reset | ||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
31 | axi_disable | AXI Disable |
RW | 0x0 | ||||||||||||||||||||||||||||||||||
28:27 | awprot | Specifies the values of the 2 EMAC AWCACHE signals. ========================== AxPROT[1] LOW: Secure Access HIGH: NonSecure Access ========================== AxPROT[0] LOW: Normal Access HIGH: Privileged Access ==========================
|
RW | 0x2 | ||||||||||||||||||||||||||||||||||
25:24 | arprot | Specifies the values of the ARPROT signals. ========================== AxPROT[1] LOW: Secure Access HIGH: NonSecure Access ========================== AxPROT[0] LOW: Normal Access HIGH: Privileged Access ==========================
|
RW | 0x2 | ||||||||||||||||||||||||||||||||||
23:20 | awcache | Specifies the values of the 2 EMAC AWCACHE signals. The field array index corresponds to the EMAC index.
|
RW | 0x0 | ||||||||||||||||||||||||||||||||||
19:16 | arcache | Specifies the values of the 2 EMAC ARCACHE signals. The field array index corresponds to the EMAC index.
|
RW | 0x0 | ||||||||||||||||||||||||||||||||||
12 | app_clk_sel | Selects the source of the Application clock for the datapath to either l4_mp_clk for normal Baum operation or to f2s_ap_clk if the switch interface is enabled to the FPGA fabric.
|
RW | 0x0 | ||||||||||||||||||||||||||||||||||
8 | ptp_ref_sel | This field selects if the Timestamp reference is internally or externally generated. EMAC0 may be the master to generate the timestamp for EMAC1 and EMAC2. EMAC0 must be set to Internal Timestamp. EMAC1/2 may be set to either Internal or External.
|
RW | 0x0 | ||||||||||||||||||||||||||||||||||
1:0 | phy_intf_sel | PHY Interface Select Field to select "Out of Reset", GMII (or MII), RGMII or RMII as the PHY interface. Note, the MAC speed is an output of Synopsys IP. So the System Manager PHY Select combined with MAC speed from the IP determine the clock/PHY configuration. "Out of Reset" mode implies that the MAC RX and TX internal clocks use the Clock Manager reference rather than depending on the PHY to have active clocks.
|
RW | 0x3 |