io48_hmc_mmr Summary

Base Address: 0xFFCFA000

Register

Address Offset

Bit Fields
i_io48_hmc_mmr_io48_mmr

dbgcfg0

0x0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cfg_dbg_mode

0x0

cfg_cmd_driver_sel

0x0

cfg_loopback_en

0x0

cfg_mmr_driver_sel

0x0

cfg_prbs_ctrl_sel

0x0

cfg_wdata_driver_sel

0x0

dbgcfg1

0x4

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

cfg_dbg_ctrl

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_dbg_ctrl

0x0

dbgcfg2

0x8

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

cfg_bist_cmd0_u

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_bist_cmd0_u

0x0

dbgcfg3

0xC

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

cfg_bist_cmd0_l

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_bist_cmd0_l

0x0

dbgcfg4

0x10

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

cfg_bist_cmd1_u

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_bist_cmd1_u

0x0

dbgcfg5

0x14

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

cfg_bist_cmd1_l

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_bist_cmd1_l

0x0

dbgcfg6

0x18

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_dbg_out_sel

0x0

reserve0

0x1C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_reserve0

0x0

reserve1

0x20

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_reserve1

0x0

reserve2

0x24

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_reserve2

0x0

ctrlcfg0

0x28

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_dbc2_burst_length

0x0

cfg_dbc1_burst_length

0x0

cfg_dbc0_burst_length

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_dbc0_burst_length

0x0

cfg_ctrl_burst_length

0x0

cfg_ac_pos

0x0

cfg_dimm_type

0x0

cfg_mem_type

0x0

ctrlcfg1

0x2C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_dbc3_enable_dm

0x0

cfg_dbc2_enable_dm

0x0

cfg_dbc1_enable_dm

0x0

cfg_dbc0_enable_dm

0x0

cfg_ctrl_enable_dm

0x0

cfg_dqstrk_en

0x0

cfg_starve_limit

0x0

cfg_reorder_read

0x0

cfg_dbc3_reorder_rdata

0x0

cfg_dbc2_reorder_rdata

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_dbc1_reorder_rdata

0x0

cfg_dbc0_reorder_rdata

0x0

cfg_ctrl_reorder_rdata

0x0

cfg_reorder_data

0x0

cfg_dbc3_enable_ecc

0x0

cfg_dbc2_enable_ecc

0x0

cfg_dbc1_enable_ecc

0x0

cfg_dbc0_enable_ecc

0x0

cfg_ctrl_enable_ecc

0x0

cfg_addr_order

0x0

cfg_dbc3_burst_length

0x0

ctrlcfg2

0x30

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_dbc3_pipe_lat

0x0

cfg_dbc2_pipe_lat

0x0

cfg_dbc1_pipe_lat

0x0

cfg_dbc0_pipe_lat

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_dbc0_pipe_lat

0x0

cfg_dbc2ctrl_sel

0x0

cfg_dbc3_ctrl_sel

0x0

cfg_dbc2_ctrl_sel

0x0

cfg_dbc1_ctrl_sel

0x0

cfg_dbc0_ctrl_sel

0x0

cfg_ctrl2dbc_switch1

0x0

cfg_ctrl2dbc_switch0

0x0

cfg_dbc3_output_regd

0x0

cfg_dbc2_output_regd

0x0

cfg_dbc1_output_regd

0x0

cfg_dbc0_output_regd

0x0

cfg_ctrl_output_regd

0x0

ctrlcfg3

0x34

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_rld3_multibank_mode

0x0

cfg_geardn_en

0x0

cfg_open_page_en

0x0

cfg_arbiter_type

0x0

cfg_dbc3_dualport_en

0x0

cfg_dbc2_dualport_en

0x0

cfg_dbc1_dualport_en

0x0

cfg_dbc0_dualport_en

0x0

cfg_ctrl_dualport_en

0x0

cfg_dbc3_in_protocol

0x0

cfg_dbc2_in_protocol

0x0

cfg_dbc1_in_protocol

0x0

cfg_dbc0_in_protocol

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_ctrl_in_protocol

0x0

cfg_dbc3_cmd_rate

0x0

cfg_dbc2_cmd_rate

0x0

cfg_dbc1_cmd_rate

0x0

cfg_dbc0_cmd_rate

0x0

cfg_ctrl_cmd_rate

0x0

ctrlcfg4

0x38

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

cfg_dbc3_slot_offset

0x0

cfg_dbc2_slot_offset

0x0

cfg_dbc1_slot_offset

0x0

cfg_dbc0_slot_offset

0x0

cfg_ctrl_slot_offset

0x0

cfg_dbc3_slot_rotate_en

0x0

cfg_dbc2_slot_rotate_en

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_dbc1_slot_rotate_en

0x0

cfg_dbc0_slot_rotate_en

0x0

cfg_ctrl_slot_rotate_en

0x0

cfg_pingpong_mode

0x0

cfg_tile_id

0x0

ctrlcfg5

0x3C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cfg_dbc3_rc_en

0x0

cfg_dbc2_rc_en

0x0

cfg_dbc1_rc_en

0x0

cfg_dbc0_rc_en

0x0

cfg_ctrl_rc_en

0x0

cfg_row_cmd_slot

0x0

cfg_col_cmd_slot

0x0

ctrlcfg6

0x40

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_cs_chip

0x0

ctrlcfg7

0x44

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cfg_wb_reserved_entry

0x0

cfg_rb_reserved_entry

0x0

cfg_clkgating_en

0x0

ctrlcfg8

0x48

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cfg_addr_mplx_en

0x0

cfg_ck_inv

0x0

cfg_3ds_en

0x0

ctrlcfg9

0x4C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cfg_dfx_bypass_en

0x0

dramtiming0

0x50

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_mem_clk_disable_entry_cycles

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_mem_clk_disable_entry_cycles

0x0

cfg_power_saving_exit_cycles

0x0

cfg_tcl

0x0

dramodt0

0x54

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

cfg_read_odt_chip

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_write_odt_chip

0x0

dramodt1

0x58

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_rd_odt_period

0x0

cfg_wr_odt_period

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_wr_odt_period

0x0

cfg_rd_odt_on

0x0

cfg_wr_odt_on

0x0

sbcfg0

0x5C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

cfg_rld3_refresh_seq1

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_rld3_refresh_seq0

0x0

sbcfg1

0x60

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

cfg_rld3_refresh_seq3

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_rld3_refresh_seq2

0x0

sbcfg2

0x64

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cfg_srf_entry_exit_block

0x0

cfg_srf_autoexit_en

0x0

cfg_user_rfsh_en

0x0

cfg_sb_cg_disable

0x0

cfg_mps_dqstrk_disable

0x0

cfg_mps_zqcal_disable

0x0

cfg_srf_zqcal_disable

0x0

sbcfg3

0x68

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_sb_ddr4_mr3

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_sb_ddr4_mr3

0x0

sbcfg4

0x6C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_sb_ddr4_mr4

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_sb_ddr4_mr4

0x0

sbcfg5

0x70

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cfg_period_dqstrk_ctrl_en

0x0

cfg_short_dqstrk_ctrl_en

0x0

sbcfg6

0x74

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

cfg_t_param_dqstrk_to_valid

0x0

cfg_t_param_dqstrk_to_valid_last

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_period_dqstrk_interval

0x0

sbcfg7

0x78

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cfg_rfsh_warn_threshold

0x0

caltiming0

0x7C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_t_param_act_to_act_diff_bg

0x0

cfg_t_param_act_to_act_diff_bank

0x0

cfg_t_param_act_to_act

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_t_param_act_to_act

0x0

cfg_t_param_act_to_pch

0x0

cfg_t_param_act_to_rdwr

0x0

caltiming1

0x80

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_t_param_rd_to_wr_diff_chip

0x0

cfg_t_param_rd_to_wr

0x0

cfg_t_param_rd_to_rd_diff_bg

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_t_param_rd_to_rd_diff_bg

0x0

cfg_t_param_rd_to_rd_diff_chip

0x0

cfg_t_param_rd_to_rd

0x0

caltiming2

0x84

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_t_param_wr_to_wr_diff_chip

0x0

cfg_t_param_wr_to_wr

0x0

cfg_t_param_rd_ap_to_valid

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_t_param_rd_ap_to_valid

0x0

cfg_t_param_rd_to_pch

0x0

cfg_t_param_rd_to_wr_diff_bg

0x0

caltiming3

0x88

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_t_param_wr_to_pch

0x0

cfg_t_param_wr_to_rd_diff_bg

0x0

cfg_t_param_wr_to_rd_diff_chip

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_t_param_wr_to_rd_diff_chip

0x0

cfg_t_param_wr_to_rd

0x0

cfg_t_param_wr_to_wr_diff_bg

0x0

caltiming4

0x8C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

cfg_t_param_pdn_to_valid

0x0

cfg_t_param_arf_to_valid

0x0

cfg_t_param_pch_all_to_valid

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_t_param_pch_all_to_valid

0x0

cfg_t_param_pch_to_valid

0x0

cfg_t_param_wr_ap_to_valid

0x0

caltiming5

0x90

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_t_param_srf_to_zq_cal

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_t_param_srf_to_zq_cal

0x0

cfg_t_param_srf_to_valid

0x0

caltiming6

0x94

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_t_param_pdn_period

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_t_param_pdn_period

0x0

cfg_t_param_arf_period

0x0

caltiming7

0x98

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_t_param_mps_to_valid

0x0

cfg_t_param_mrs_to_valid

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_t_param_zqcs_to_valid

0x0

cfg_t_param_zqcl_to_valid

0x0

caltiming8

0x9C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_t_param_mmr_cmd_to_valid

0x0

cfg_t_param_rld3_multibank_ref_delay

0x0

cfg_t_param_mps_exit_cke_to_cs

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_t_param_mps_exit_cke_to_cs

0x0

cfg_t_param_mps_exit_cs_to_cke

0x0

cfg_t_param_mpr_to_valid

0x0

cfg_t_param_mrr_to_valid

0x0

caltiming9

0xA0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cfg_t_param_4_act_to_act

0x0

caltiming10

0xA4

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cfg_t_param_16_act_to_act

0x0

dramaddrw

0xA8

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_cs_addr_width

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_bank_group_addr_width

0x0

cfg_bank_addr_width

0x0

cfg_row_addr_width

0x0

cfg_col_addr_width

0x0

sideband0

0xAC

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

mr_cmd_trigger

0x0

sideband1

0xB0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

mmr_refresh_req

0x0

sideband2

0xB4

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

mmr_zqcal_long_req

0x0

sideband3

0xB8

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

mmr_zqcal_short_req

0x0

sideband4

0xBC

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

mmr_self_rfsh_req

0x0

sideband5

0xC0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

mmr_dpd_mps_req

0x0

sideband6

0xC4

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

mr_cmd_ack

0x0

sideband7

0xC8

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

mmr_refresh_ack

0x0

sideband8

0xCC

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

mmr_zqcal_ack

0x0

sideband9

0xD0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

mmr_self_rfsh_ack

0x0

sideband10

0xD4

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

mmr_dpd_mps_ack

0x0

sideband11

0xD8

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

mmr_auto_pd_ack

0x0

sideband12

0xDC

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

mr_cmd_rank

0x0

mr_cmd_type

0x0

sideband13

0xE0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

mr_cmd_opcode

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

mr_cmd_opcode

0x0

sideband14

0xE4

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

mmr_refresh_bank

0x0

sideband15

0xE8

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

mmr_stall_rank

0x0

dramsts

0xEC

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

phy_cal_fail

0x0

phy_cal_success

0x0

dbgdone

0xF0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

dbg_done

0x0

dbgsignals

0xF4

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

dbg_signals_out

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

dbg_signals_out

0x0

dbgreset

0xF8

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

counter_one_reset

0x0

counter_zero_reset

0x0

dbgmatch

0xFC

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

counter_one

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

counter_zero

0x0

counter0mask

0x100

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

counter_zero_mask

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

counter_zero_mask

0x0

counter1mask

0x104

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

counter_one_mask

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

counter_one_mask

0x0

counter0match

0x108

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

counter_zero_match

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

counter_zero_match

0x0

counter1match

0x10C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

counter_one_match

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

counter_one_match

0x0

niosreserve0

0x110

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

nios_reserve0

0x0

niosreserve1

0x114

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

nios_reserve1

0x0

niosreserve2

0x118

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

nios_reserve2

0x0