module two_controllers ( // Top Controller // inputs: ddr2_top_fedback_clk_in, // outputs: ddr2_top_clk_to_sdram, ddr2_top_clk_to_sdram_n, ddr2_top_a, ddr2_top_ba, ddr2_top_cas_n, ddr2_top_cke, ddr2_top_cs_n, ddr2_top_dm, ddr2_top_dq, ddr2_top_dqs, ddr2_top_odt, ddr2_top_ras_n, ddr2_top_we_n, ddr2_top_fedback_clk_out, pnf_top, // Bottom Controller // inputs: ddr2_bottom_fedback_clk_in, // outputs: ddr2_bottom_clk_to_sdram, ddr2_bottom_clk_to_sdram_n, ddr2_bottom_a, ddr2_bottom_ba, ddr2_bottom_cas_n, ddr2_bottom_cke, ddr2_bottom_cs_n, ddr2_bottom_dm, ddr2_bottom_dq, ddr2_bottom_dqs, ddr2_bottom_odt, ddr2_bottom_ras_n, ddr2_bottom_we_n, ddr2_bottom_fedback_clk_out, pnf_bottom, // Common Signals clock_source, reset_n, pnf_per_byte, test_complete); output pnf_top; output pnf_bottom; // Common signals output [ 7: 0] pnf_per_byte; output test_complete; input clock_source; input reset_n; // Top Controller output [ 0: 0] ddr2_top_clk_to_sdram; output [ 0: 0] ddr2_top_clk_to_sdram_n; output [ 12: 0] ddr2_top_a; output [ 2: 0] ddr2_top_ba; output ddr2_top_cas_n; output [ 0: 0] ddr2_top_cke; output [ 0: 0] ddr2_top_cs_n; output [ 3: 0] ddr2_top_dm; inout [ 31: 0] ddr2_top_dq; inout [ 3: 0] ddr2_top_dqs; output [ 0: 0] ddr2_top_odt; output ddr2_top_ras_n; output ddr2_top_we_n; output ddr2_top_fedback_clk_out; input ddr2_top_fedback_clk_in; wire ddr2_top_clk; wire [ 0: 0] ddr2_top_clk_to_sdram; wire [ 0: 0] ddr2_top_clk_to_sdram_n; wire [ 12: 0] ddr2_top_a; wire [ 2: 0] ddr2_top_ba; wire ddr2_top_cas_n; wire [ 0: 0] ddr2_top_cke; wire [ 0: 0] ddr2_top_cs_n; wire [ 3: 0] ddr2_top_dm; wire [ 31: 0] ddr2_top_dq; wire [ 3: 0] ddr2_top_dqs; wire [ 24: 0] ddr2_top_local_addr; wire [ 7: 0] ddr2_top_local_be; wire [ 9: 0] ddr2_top_local_col_addr; wire ddr2_top_local_cs_addr; wire [ 63: 0] ddr2_top_local_rdata; wire ddr2_top_local_rdata_valid; wire ddr2_top_local_read_req; wire ddr2_top_local_ready; wire ddr2_top_local_refresh_req; wire [ 1: 0] ddr2_top_local_size; wire [ 63: 0] ddr2_top_local_wdata; wire ddr2_top_local_wdata_req; wire ddr2_top_local_write_req; wire [ 0: 0] ddr2_top_odt; wire ddr2_top_ras_n; wire ddr2_top_we_n; wire ddr2_top_dedicated_postamble_clk; wire ddr2_top_dedicated_resynch_or_capture_clk; wire [ 5: 0] ddr2_top_dqs_delay_ctrl; wire ddr2_top_dqs_ref_clk; wire ddr2_top_dqsupdate; wire ddr2_top_fedback_clk_out; wire ddr2_top_fedback_resynch_clk; wire pnf_top; wire [ 7: 0] pnf_per_byte; wire ddr2_top_stratix_dll_control; wire test_complete; wire ddr2_top_write_clk; // Bottom Controller output [ 0: 0] ddr2_bottom_clk_to_sdram; output [ 0: 0] ddr2_bottom_clk_to_sdram_n; output [ 12: 0] ddr2_bottom_a; output [ 2: 0] ddr2_bottom_ba; output ddr2_bottom_cas_n; output [ 0: 0] ddr2_bottom_cke; output [ 0: 0] ddr2_bottom_cs_n; output [ 3: 0] ddr2_bottom_dm; inout [ 31: 0] ddr2_bottom_dq; inout [ 3: 0] ddr2_bottom_dqs; output [ 0: 0] ddr2_bottom_odt; output ddr2_bottom_ras_n; output ddr2_bottom_we_n; output ddr2_bottom_fedback_clk_out; // output [ 7: 0] pnf_per_byte; // output test_complete; // input clock_source; input ddr2_bottom_fedback_clk_in; // input reset_n; wire [ 0: 0] ddr2_bottom_clk_to_sdram; wire [ 0: 0] ddr2_bottom_clk_to_sdram_n; wire [ 12: 0] ddr2_bottom_a; wire [ 2: 0] ddr2_bottom_ba; wire ddr2_bottom_cas_n; wire [ 0: 0] ddr2_bottom_cke; wire [ 0: 0] ddr2_bottom_cs_n; wire [ 3: 0] ddr2_bottom_dm; wire [ 31: 0] ddr2_bottom_dq; wire [ 3: 0] ddr2_bottom_dqs; wire [ 24: 0] ddr2_bottom_local_addr; wire [ 7: 0] ddr2_bottom_local_be; wire [ 9: 0] ddr2_bottom_local_col_addr; wire ddr2_bottom_local_cs_addr; wire [ 63: 0] ddr2_bottom_local_rdata; wire ddr2_bottom_local_rdata_valid; wire ddr2_bottom_local_read_req; wire ddr2_bottom_local_ready; wire ddr2_bottom_local_refresh_req; wire [ 1: 0] ddr2_bottom_local_size; wire [ 63: 0] ddr2_bottom_local_wdata; wire ddr2_bottom_local_wdata_req; wire ddr2_bottom_local_write_req; wire [ 0: 0] ddr2_bottom_odt; wire ddr2_bottom_ras_n; wire ddr2_bottom_we_n; wire ddr2_bottom_dedicated_postamble_clk; wire ddr2_bottom_dedicated_resynch_or_capture_clk; wire [ 5: 0] ddr2_bottom_dqs_delay_ctrl; wire ddr2_bottom_dqs_ref_clk; wire ddr2_bottom_dqsupdate; wire ddr2_bottom_fedback_clk_out; wire ddr2_bottom_fedback_resynch_clk; wire pnf_bottom; wire ddr2_bottom_stratix_dll_control; // wire test_complete; wire ddr2_bottom_write_clk; // New definitions wire [ 7: 0] pnf_per_byte_top; wire [ 7: 0] pnf_per_byte_bottom; assign ddr2_top_local_refresh_req = 1'b0; assign ddr2_bottom_local_refresh_req = 1'b0; ddr2_top ddr2_top_ddr_sdram ( .clk (ddr2_top_clk), .clk_to_sdram (ddr2_top_clk_to_sdram[0 : 0]), .clk_to_sdram_n (ddr2_top_clk_to_sdram_n[0 : 0]), .ddr2_a (ddr2_top_a), .ddr2_ba (ddr2_top_ba), .ddr2_cas_n (ddr2_top_cas_n), .ddr2_cke (ddr2_top_cke), .ddr2_cs_n (ddr2_top_cs_n), .ddr2_dm (ddr2_top_dm[3 : 0]), .ddr2_dq (ddr2_top_dq), .ddr2_dqs (ddr2_top_dqs[3 : 0]), .ddr2_odt (ddr2_top_odt), .ddr2_ras_n (ddr2_top_ras_n), .ddr2_we_n (ddr2_top_we_n), .dqs_delay_ctrl (ddr2_top_dqs_delay_ctrl), .dqsupdate (ddr2_top_dqsupdate), .fedback_clk_out (ddr2_top_fedback_clk_out), .fedback_resynch_clk (ddr2_top_fedback_resynch_clk), .local_addr (ddr2_top_local_addr), .local_be (ddr2_top_local_be), .local_init_done (), .local_rdata (ddr2_top_local_rdata), .local_rdata_valid (ddr2_top_local_rdata_valid), .local_rdvalid_in_n (), .local_read_req (ddr2_top_local_read_req), .local_ready (ddr2_top_local_ready), .local_refresh_ack (), .local_size (ddr2_top_local_size), .local_wdata (ddr2_top_local_wdata), .local_wdata_req (ddr2_top_local_wdata_req), .local_write_req (ddr2_top_local_write_req), .postamble_clk (ddr2_top_dedicated_postamble_clk), .reset_n (reset_n), .resynch_clk (ddr2_top_dedicated_resynch_or_capture_clk), .stratix_dll_control (ddr2_top_stratix_dll_control), .write_clk (ddr2_top_write_clk) ); //<< END MEGAWIZARD INSERT WRAPPER_NAME //<< START MEGAWIZARD INSERT CS_ADDR_MAP //connect up the column address bits assign ddr2_top_local_addr[8 : 0] = ddr2_top_local_col_addr[9 : 1]; //<< END MEGAWIZARD INSERT CS_ADDR_MAP //<< START MEGAWIZARD INSERT EXAMPLE_DRIVER //Self-test, synthesisable code to exercise the DDR SDRAM Controller ddr2_top_example_driver driver_top ( .clk (ddr2_top_clk), .local_bank_addr (ddr2_top_local_addr[24 : 22]), .local_be (ddr2_top_local_be), .local_col_addr (ddr2_top_local_col_addr), .local_cs_addr (ddr2_top_local_cs_addr), .local_rdata (ddr2_top_local_rdata), .local_rdata_valid (ddr2_top_local_rdata_valid), .local_read_req (ddr2_top_local_read_req), .local_ready (ddr2_top_local_ready), .local_row_addr (ddr2_top_local_addr[21 : 9]), .local_size (ddr2_top_local_size), .local_wdata (ddr2_top_local_wdata), .local_wdata_req (ddr2_top_local_wdata_req), .local_write_req (ddr2_top_local_write_req), .pnf_per_byte (pnf_per_byte_top), .pnf_persist (pnf_top), .reset_n (reset_n), .test_complete (test_complete_top) ); //<< END MEGAWIZARD INSERT EXAMPLE_DRIVER //<< START MEGAWIZARD INSERT PLL ddr_pll_stratixii g_stratixpll_ddr_pll_inst_top ( .c0 (ddr2_top_clk), .c1 (ddr2_top_write_clk), .c2 (ddr2_top_dedicated_resynch_or_capture_clk), .inclk0 (clock_source) ); ddr_pll_fb_stratixii g_stratixpll_ddr_fedback_pll_inst_top ( .c0 (ddr2_top_fedback_resynch_clk), .c1 (ddr2_top_dedicated_postamble_clk), .inclk0 (ddr2_top_fedback_clk_in) ); ddr2_top_auk_ddr_dll dll_top ( .clk (dqs_ref_clk_top), .delayctrlout (ddr2_top_dqs_delay_ctrl), .dqsupdate (ddr2_top_dqsupdate), .reset_n (reset_n), .stratix_dll_control (ddr2_top_stratix_dll_control) ); assign dqs_ref_clk_top = ddr2_top_fedback_resynch_clk; // Bottom Controller ddr2_bottom ddr2_bottom_ddr_sdram ( .clk (ddr2_bottom_clk), .clk_to_sdram (ddr2_bottom_clk_to_sdram[0 : 0]), .clk_to_sdram_n (ddr2_bottom_clk_to_sdram_n[0 : 0]), .ddr2_a (ddr2_bottom_a), .ddr2_ba (ddr2_bottom_ba), .ddr2_cas_n (ddr2_bottom_cas_n), .ddr2_cke (ddr2_bottom_cke), .ddr2_cs_n (ddr2_bottom_cs_n), .ddr2_dm (ddr2_bottom_dm[3 : 0]), .ddr2_dq (ddr2_bottom_dq), .ddr2_dqs (ddr2_bottom_dqs[3 : 0]), .ddr2_odt (ddr2_bottom_odt), .ddr2_ras_n (ddr2_bottom_ras_n), .ddr2_we_n (ddr2_bottom_we_n), .dqs_delay_ctrl (ddr2_bottom_dqs_delay_ctrl), .dqsupdate (ddr2_bottom_dqsupdate), .fedback_clk_out (ddr2_bottom_fedback_clk_out), .fedback_resynch_clk (ddr2_bottom_fedback_resynch_clk), .local_addr (ddr2_bottom_local_addr), .local_be (ddr2_bottom_local_be), .local_init_done (), .local_rdata (ddr2_bottom_local_rdata), .local_rdata_valid (ddr2_bottom_local_rdata_valid), .local_rdvalid_in_n (), .local_read_req (ddr2_bottom_local_read_req), .local_ready (ddr2_bottom_local_ready), .local_refresh_ack (), .local_size (ddr2_bottom_local_size), .local_wdata (ddr2_bottom_local_wdata), .local_wdata_req (ddr2_bottom_local_wdata_req), .local_write_req (ddr2_bottom_local_write_req), .postamble_clk (ddr2_bottom_dedicated_postamble_clk), .reset_n (reset_n), .resynch_clk (ddr2_bottom_dedicated_resynch_or_capture_clk), .stratix_dll_control (ddr2_bottom_stratix_dll_control), .write_clk (ddr2_bottom_write_clk) ); //connect up the column address bits assign ddr2_bottom_local_addr[8 : 0] = ddr2_bottom_local_col_addr[9 : 1]; //<< START MEGAWIZARD INSERT EXAMPLE_DRIVER //Self-test, synthesisable code to exercise the DDR SDRAM Controller ddr2_bottom_example_driver driver_bottom ( .clk (ddr2_bottom_clk), .local_bank_addr (ddr2_bottom_local_addr[24 : 22]), .local_be (ddr2_bottom_local_be), .local_col_addr (ddr2_bottom_local_col_addr), .local_cs_addr (ddr2_bottom_local_cs_addr), .local_rdata (ddr2_bottom_local_rdata), .local_rdata_valid (ddr2_bottom_local_rdata_valid), .local_read_req (ddr2_bottom_local_read_req), .local_ready (ddr2_bottom_local_ready), .local_row_addr (ddr2_bottom_local_addr[21 : 9]), .local_size (ddr2_bottom_local_size), .local_wdata (ddr2_bottom_local_wdata), .local_wdata_req (ddr2_bottom_local_wdata_req), .local_write_req (ddr2_bottom_local_write_req), .pnf_per_byte (pnf_per_byte_bottom), .pnf_persist (pnf_bottom), .reset_n (reset_n), .test_complete (test_complete_bottom) ); assign pnf_per_byte = pnf_per_byte_top | pnf_per_byte_bottom; assign test_complete = test_complete_top | test_complete_bottom; //<< END MEGAWIZARD INSERT EXAMPLE_DRIVER //<< START MEGAWIZARD INSERT PLL ddr_bottom_pll_stratixii g_stratixpll_ddr_pll_inst_bottom ( .c0 (ddr2_bottom_clk), .c1 (ddr2_bottom_write_clk), .c2 (ddr2_bottom_dedicated_resynch_or_capture_clk), .inclk0 (clock_source) ); ddr_bottom_pll_fb_stratixii g_stratixpll_ddr_fedback_pll_inst_bottom ( .c0 (ddr2_bottom_fedback_resynch_clk), .c1 (ddr2_bottom_dedicated_postamble_clk), .inclk0 (ddr2_bottom_fedback_clk_in) ); //------------------------------------------------------------ //Instantiate Stratix Series DLL for Read DQS Phase shift //------------------------------------------------------------ ddr2_bottom_auk_ddr_dll dll_bottom ( .clk (dqs_ref_clk_bottom), .delayctrlout (ddr2_bottom_dqs_delay_ctrl), .dqsupdate (ddr2_bottom_dqsupdate), .reset_n (reset_n), .stratix_dll_control (ddr2_bottom_stratix_dll_control) ); assign dqs_ref_clk_bottom = ddr2_bottom_fedback_resynch_clk; endmodule