ALTERA DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED IN THIS PATCH WILL MEET YOUR REQUIREMENTS, OR THAT THE OPERATION OF THIS PATCH WILL BE UNINTERRUPTED OR ERROR-FREE. //**************************************************************** quartusii-12.0sp2-2.dp9-readme.txt Readme file for Quartus II 12.0 SP2 Patch 2.dp9 Copyright (C) Altera Corporation 2012 All right reserved. Patch created on October 25 2012 Patch case#: 70292 //**************************************************************** Please note, this patch is meant to address known software issues for Stratix V, Arria V and Cyclone V devices in the Quartus II software version 12.0 SP2. The device patches are cumulative. ====================================== The following were addressed in 2.dp2: ====================================== -------------------- Issue 1 (case 65815) -------------------- This patch allows designs to see the association between the DSP enable signal and the input registers for Arria V devices. -------------------- Issue 2 (case 66224) -------------------- This patch enables POF support for Stratix V 5SGXEB5, 5SGXEB6, 5SGXMB5, and 5SGXMB6 devices. -------------------- Issue 3 (case 66618) -------------------- If an Arria V GX parts has both datarate larger than 3125Mbps and smaller than 3125Mbps, the transceiver voltage is 1.1V for datarate smaller than 3125Mbps and 1.15V for datarate larger than 3125Mbps. This resulted a clash of voltages on VCCR/VCCT when using datarate above and below 3125Mbps. -------------------- Issue 4 (case 67678) -------------------- This patch updates Stratix V OCT calibration block settings in Quartus II software to match changes in Rref resistance from 2 KOhm to 1.8 KOhm. New settings also applies to Stratix V GT channels. Instructions: User must regenerate Quartus II Software IP files and recompile his/her design for this patch to take effect: 1.On a Qsys-based design, by opening the design in Qsys, (re)generating the files and recompiling. 2.On a Megawizard-based design, by opening the existing Megawizard design, (re)generating the files and recompiling. -------------------- Issue 5 (case 69027) -------------------- This patch enables POF support for Arria V 500GT/GX devices. -------------------- Issue 6 (case 69480) -------------------- The Fitter may not consistently promote all clock edges in a clock domain to use dedicated clock routing, if any of its destination registers are used to generate additional clock or control signals. This patch addresses this issue, and should reduce clock skew on the affected clock domain(s). The following INI is required to enable this change: fsv_adjust_clock_promotion_behavior=on -------------------- Issue 7 (case 69534) -------------------- Quartus II triggers the following Internal Error in Fitter stage: Internal Error: Sub-system: FSV, File: /quartus/fitter/fsv/fsv_module_mint_dq_grouping.cpp Line: 1179 (*group_query).second == id -------------------- Issue 8 (case 69608) -------------------- This patch enables POF support for Stratix V 5SGXEB5R2F43I3 device ====================================== The following were addressed in 2.dp3: ====================================== -------------------- Issue 9 (case 71185) -------------------- This patch fixes connectivity from CLKPINs to right-corner QCLKs on Cyclone V devices. -------------------- Issue 10 (case 69809) -------------------- Many checks are done on RAM blocks to ensure LUTRAM conversion is possible. One of these checks is done to prevent functional differences between the converted LUTRAM and the original block RAM. There is an issue caught in 12.0sp2 so the RAM blocks that have their read address clock set to clock1 are disabled. This may cause designs which used to rely on LUTRAM conversion for these type of RAM blocks to no-fit. This issue affects Stratix III/IV/V, Arria V, Cyclone V devices. This patch provides two fixes for this issue: 1. There is actually no functional difference if both clock0 and clock1 were driven by the same clock signal. Thus the constraint is relaxed to allow for this case. 2. The functional difference only occurs during a rare accidental read-during-write. If you are aware of the differences between block RAMs and LUTRAMs, Altera provides the ability to turn this constraint off by using the following INI: allow_port_b_read_address_clk_for_lutram_conversion=on -------------------- Issue 11 (case 70771) -------------------- This patch enables POF support for Arria V 360 GT/GX devices. -------------------- Issue 12 (case 69659) -------------------- Some circuits may experience non-optimal pipeline placement. In some scenario, the final placement does not have the pipeline registers evenly spaced out, and may lead to timing failure on the pipeline transfer that is placed farther apart. This patch provides an enhancement on the pipeline placement, such that fitter will be trying to balance the register pipelines more intelligently. This enhancement is INI-protected. You need to use the following INI to enable this feature: vpr_place_enable_sr_dynamic_adjustment=on -------------------- Issue 13 (case 69532) -------------------- This patch allows you to select high-effort as well as power-based exploration options in DSE for projects targeting Cyclone IV, Cyclone V, and Arria V devices. ====================================== The following were addressed in 2.dp4: ====================================== -------------------- Issue 14 (case 68707) -------------------- This patch supports -4 timing model for Arria V B3 ES devices. -------------------- Issue 15 (case 70109) -------------------- For Stratix V ddio_out functional simulation, user may encounter visible glitches due to delta cycle delays. This patch removes the glitch from functional simulation model. -------------------- Issue 16 (case 71749) -------------------- The tx pulse will be correctly stretched when simulating the Seriallite-III IP. This applies to Stratix V devices only. -------------------- Issue 17 (case 72574) -------------------- Quartus II software triggers the following Internal Error when running compilation after doing "Update Symbol or Block..." in Block Editor. Internal Error: Sub-system: DBMUI, File: /quartus/db/dbmui/dbmui_manager.cpp, Line: 1179 Attempt made to free all hierarchy databases but the following callers are still accessing it: GEDQ_VIEW::get_sld_hdb_iname, ====================================== The following were addressed in 2.dp5: ====================================== -------------------- Issue 18 (case 72575) -------------------- Quartus II software triggers the following Internal Error when trying to generate POF for Arria V B3 devices: Internal Error: Sub-system: ASM, File: /quartus/comp/asm/asm_caddy_arria5.cpp, Line: 402 Unknown hmcphy_int instance name -------------------- Issue 19 (case 63553) -------------------- This patch allows you to export a version compatible database for projects targeting to Stratix V devices that are not officially supported. You can later import the version compatible database back to Quartus II version 12.1. This feature is under INI control, please contact Altera FAE/AE if you need to use this feature. -------------------- Issue 20 (case 73322) -------------------- Attention to PCI Express Compiler users, this patch includes: 1. Hard reset controller fixes and analog setting modifications to reliably operate PCIe Gen2 across all platforms. 2. Soft reset controller fixes and analog setting modifications to reliably operate PCIe Gen3 across all platforms. Please follow these steps to successfully apply this fix. * Add the following QSF settings set_instance_assignment -name XCVR_RX_SD_ON 1 -to set_instance_assignment -name XCVR_RX_SD_OFF 5 -to set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to * The PHY IP reconfiguration controller must be connected to the PCIe IP G1/G2 : Use offset cancellation ON G3 : Use offset cancellation ON and AEQ ON * Regenerate PCIe IP * Recompile the design Please note, if you're not using PCIe, you're not affected by this fix. Please contact Altera FAE/AE if you need more info or help on this. -------------------- Issue 21 (case 73561) -------------------- Quartus II software triggers the following Internal Error in Assembler: Internal Error: Sub-system: ASMGX, File: /quartus/comp/asmgx/asmgx_stratixv.cpp, Line: 480 bus_line != -1 -------------------- Issue 22 (case 73696) -------------------- This patch enables POF support for Stratix V 5SGXMA9 and 5SGXEA9 devices. You need to use the dev_password to enable the support. Please put the device password statement(s) in quartus.ini, and put quartus.ini into your project directory. You can use variables dev_password0 through dev_password9. If you have any existing dev_password in your quartus.ini file, make sure the variable names do not overlap. #Target Parts: #5SGXEA9N1F45C2 #5SGXEA9N1F45I2 #5SGXEA9N2F45C2 #5SGXEA9N2F45I2 #5SGXEA9N3F45C2 #5SGXEA9N2F45C3 #5SGXEA9N2F45I3 #5SGXEA9N3F45C3 #5SGXEA9N3F45I3 #5SGXEA9N3F45C4 #5SGXEA9N3F45I4 dev_password0 = d0070c637d8467d235c5451239a66a9726b57508f88dbba0bfc64e9a8ec32f3256ed8122336132242223571105214345530332511222445555152271225455575444165444 #Target Parts: #5SGXMA9N1F45C2 #5SGXMA9N1F45I2 #5SGXMA9N2F45C2 #5SGXMA9N2F45I2 #5SGXMA9N3F45C2 #5SGXMA9N2F45C3 #5SGXMA9N2F45I3 #5SGXMA9N3F45C3 #5SGXMA9N3F45I3 #5SGXMA9N3F45C4 #5SGXMA9N3F45I4 dev_password1 = d0070c637d8467d235c5451239a66a9f26b57508f88dbba0bfc64e9a8ec32f3256ed8122336132242223571105214345530332511222445555152271225455575444165444 -------------------- Issue 23 (case 73749) -------------------- Quartus II software may trigger the following Fatal Error when programming the device using SignalTap. *** Fatal Error: Access Violation at 0X0000000000DC2CDB Module: quartus.exe Stack Trace: 0x2cda: MSG_REPORT_FILE::close_stream_if_open + 0x22a (CCL_MSG) 0xf607: TclInvokeStringCommand + 0xc7 (tcl85) -------------------- Issue 24 (case 73851) -------------------- This patch updates connectivity from bottom CLKPINs to bottom-right corner QCLKs on Cyclone V devices. ====================================== The following were addressed in 2.dp6: ====================================== -------------------- Issue 25 (case 74054) -------------------- This patch enables POF support for Arria V 5AGTFH3F35I3AB device. You need to use the dev_password to enable the support. Please put the device password statement(s) in quartus.ini, and put quartus.ini into your project directory. You can use variables dev_password0 through dev_password9. If you have any existing dev_password in your quartus.ini file, make sure the variable names do not overlap. dev_password2 = d0070c637d8802a600c037807b0336663a870c56097b844c137c3267766704eb0aa28584c2b0ba7577008d2223efc6ebf71a5c01d5fb7805ed13ede8122336132243233372337721110437224252000114200511057522222572322163254455551422602222222133236152010111040551755554557455 -------------------- Issue 26 (case 74490) -------------------- Quartus II software may trigger the following Fatal Error when the partition merge phase would run on only a single partition. *** Fatal Error: Access Violation at 0X0174836C Module: quartus_map.exe Stack Trace: 0x5b236:HDB_INSTANCE_NAME::wildcard_resolution + 0x22 (DB_HDB) 0x5fa05:HDB_OPTION::relative_resolution + 0x35 (DB_HDB) 0x2c046:HDB_OPTION::get_option + 0x36 (DB_HDB) -------------------- Issue 27 (case 74541) -------------------- In fractional PLL case, analog simulation caused VCO period to be slightly off while trying to sync with refclk due to simulation precision issues. This caused lock to deassert in long simulations. This patch updates the simulation model such that VCO is consistent period and lock is not deasserted during extensive simulation. -------------------- Issue 28 (case 74777) -------------------- A VHDL feature is that when using a deferred constant in a package, that constant is initialized in the body of the package rather than in the package declaration itself. For constants which are of type unconstraint arrays where the range and the direction is being set during the initialization Quartus had a bug where the range was not setup correctly. ====================================== The following were addressed in 2.dp7: ====================================== -------------------- Issue 29 (case 75245) -------------------- This patch fixes the placement preservation issue for hard block atoms such as PLLs, when imported from a QXP. The QXP partition needs to be recompiled and exported with this patch. For this patch the following INI is also needed to ensure such preservation: rcf_show_gid_map=on Affected devices: Stratix V -------------------- Issue 30 (case 75362) -------------------- Quartus II software incorrectly uses post-synthesis data instead of post-fitter data. As a result the rom part for controlling physical to logical mapping is incorrect in the generated SOF file. Affected devices: Arria V, Cyclone V, Stratix V -------------------- Issue 31 (case 75728) -------------------- An error is encountered while compiling a Persona revision for a Partial Reconfiguration (PR) project due to hard-routing constraints not being satisfiable. The patch improves the dedicated signal detection code such that the same signals are detected on the persona compile as the static compile which allows the static partition to be preserved properly. Affected devices: Arria V, Cyclone V, Stratix V -------------------- Issue 32 (case 75931) -------------------- Incorrect Interlaken PCS Settings on Stratix V devices with 36 or 66 transceivers from the following list below: 5SGSD4K**40, 5SGSD5K**40, 5SGXA3K**35, 5SGXA3K**40, 5SGXA4K**35, 5SGXA4K**40, 5SGXB5R**40, 5SGXB5R**43, 5SGXB6R**40, 5SGXB6R**43, 5SGXB9R**43, and 5SGXBBR**43 Affected devices: Stratix V -------------------- Issue 33 (case 75933) -------------------- This patch provides a workaround for expected PLL simulation in NCSim. For PLLs with "Reconfigurable" subtype, resetting the PLL will output the expected clock frequencies in simulation. Affected devices: Arria V, Stratix V -------------------- Issue 34 (case 77360) -------------------- This patch enables POF support for Stratix V 5SGXEA9, 5SGXMA9, 5SGXMAB, 5SGXEAB, 5SGXEBB(1760 package only) devices. You need to use the dev_password to enable the support. Please put the device password statement(s) in quartus.ini, and put quartus.ini into your project directory. You can use variables dev_password0 through dev_password9. If you have any existing dev_password in your quartus.ini file, make sure the variable names do not overlap. #Devices = 5SGXEA9 dev_password3 = d0070c637d8467d235c5451239a66a9726b57508f2a06f112b729e333913403c812233613224222357110521434553033251122244552273221755545546545406 #Devices = 5SGXMA9 dev_password4 = d0070c637d8467d235c5451239a66a9f26b57508f2a06f112b729e333913403c812233613224222357110521434553033251122244552273221755545546545406 #Devices = 5SGXMAB dev_password5 = d0070c637d8467d235c5451239a66a9f2db57508f2a06f112b729e333913403c812233613224222357110521434553033221122244552273221755545546545406 #Devices = 5SGXEAB dev_password6 = d0070c637d8467d235c5451239a66a972db57508f2a06f112b729e333913403c812233613224222357110521434553033221122244552273221755545546545406 #Devices = 5SGXEBB (1760 pacakge only) dev_password7 = d0070c637d8467d235c5451239a66a971db57508f8689ba0bfc64e9a8ec32f3256ed8122336132242223571105214345530332211222445555152271225455575444165444 Affected devices: Stratix V ====================================== The following were addressed in 2.dp8: ====================================== -------------------- Issue 35 (case 77990) -------------------- Quartus II triggers the following Internal Error in Assembler: Internal Error: Sub-system: ASMIO, File: /quartus/comp/asmio/asmio_leveling.cpp, Line: 933 Unexpected phyclk Location The problem is that Quartus II Assemble does not allow a valid clock phyclk Location for the Stratix V 5SGXEABN2 devices (All F7 and F9 devices). This only happens for the corner phyclk location, the center phyclk location is not affected. This patch allows and properly configures the phyclk placed at the corners of the affected devices. Affected devices: Stratix V -------------------- Issue 36 (case 76697) -------------------- Quartus II triggers the following Internal Error in Assembler: Internal Error: Sub-system: ASM, File: /quartus/comp/asm/asm_pr_bits_utility.cpp, Line: 1143 ASM_PR_BITS_UTILITY::compare_masked_byte_array This problem happens to designs using incremental compilation with post_fit partitions, and possibly more common with partial reconfig flow. Affected devices: Arria V, Cyclone V, Stratix V -------------------- Issue 37 (case 77880) -------------------- Quartus II triggers the following Internal Error during compilation: Internal Error: Sub-system: CUT, File: /quartus/db/cut/cut_atom_util.cpp, Line: 307 matched_atom == 0 The problem is due to a logical connection issue with Quartus II Fitter when it tries to rewire the control plane bonding channels together with dummy channel. Affected devices: Arria V, Cyclone V ====================================== The following were addressed in 2.dp9: ====================================== -------------------- Issue 38 (case 69816) -------------------- This patch fixes a potential non-determinism issue in the Quartus II Fitter that can arise in early routing iterations. Affected devices: All families -------------------- Issue 39 (case 78452) -------------------- This patch updates CDR setting for operation above 12.5Gbps RX. Affected devices: Stratix V -------------------- Issue 40 (case 79571) -------------------- This patch provides device support for Cyclone V 5CGTFD7C5U19C7ES under dev_password control. Please contact Altera if you need support for that device. Affected devices: Cyclone V -------------------- Issue 41 (case 79721) -------------------- When executing a CPRI read using the CPU interface, the data read back is sometimes incorrect. This issue will occur although rare when the cpu_clk clock frequency used is higher than the core clock cpri_clkout. Affected devices: All devices supporting CPRI -------------------- Issue 42 (case 79722) -------------------- CPRI core stops transmitting the radio frame after one hour. Affected devices: All devices supporting CPRI -------------------- Issue 43 (case 80017) -------------------- This patch adds a soft IP to address high ICC for Arria V and Cyclone V production devices + CV A7ES/C7ES and AV B3ES devices. Affected devices: Arria V, Cyclone V -------------------- Issue 44 (case 80367) -------------------- If a PLL is used to drive two DQS groups, one of the DQS group would fail to receive the clock signal. This patch fixes this problem. Affected devices: Cyclone V Caution - You must either have previously installed the Quartus II 12.0 SP2 software or must install the Quartus II 12.0 SP2 software before installing this patch. Otherwise, the patch will not be installed correctly and the Quartus II software will not run properly.