Advanced System Design Using Platform Designer: System Optimization (OAQSYSOPT)

46 Minutes Online Course

Course Description

This training is part 3 of 4. The Platform Designer system integration tool saves significant time by automatically generating interconnect logic to connect intellectual property (IP) functions and subsystems. In this training you will learn about some advanced capabilities of the tool. In the third part, you will learn about how Platform Designer builds its interconnect for your unique design and why the generated results might not always meet timing or performance requirements. Platform Designer automatically adds adapters to allow different components to communicate with each other, and these adapters may affect timing in the system. You'll learn techniques you can use to improve system performance, from standard interface design to the addition of pipeline bridges.

At Course Completion

You will be able to:

  • Understand why and how timing issues can occur in Platform Designer systems
  • Use techniques to improve system performance
  • Implement changes in a system's topology through the addition of pipeline bridges that can help close timing

Skills Required

  • Background in digital logic design
  • Familiarity with the Intel® Quartus® Prime software
  • Familiarity with the Platform Designer system design tool

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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