PCI Express IP – Support Center

Welcome to the PCI Express (PCIe) IP support center!

Here you will find information on how to select, design, and implement PCIe links. There are also guidelines on how to bring up your system and debug the PCIe links. This page is organized into categories that align with a PCIe system design flow from start to finish.  

Enjoy your journey!

Get support resources for Intel® Agilex™, Intel Stratix® 10, Intel Arria® 10, and Intel Cyclone® 10 devices from the pages below. For other devices, search from the following links: Documentation Archive, Training Courses, Videos and Webcasts, Design Examples, Knowledge Base.

Refer to Table 1 and Table 2 to understand the PCIe support for Intel® FPGAs. Compare between the devices to select the right device for your PCIe system implementation.

Intel® Agilex, Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 Device for PCIe

The PCIe IP solutions encompass Intel’s technology-leading PCIe hardened protocol stack that includes the transaction and data link layers; and hardened physical layer, which includes both the physical medium attachment (PMA) and physical coding sublayer (PCS). Intel's PCIe IP also includes optional blocks, such as direct memory access (DMA) engines and single root I/O virtualization (SR-IOV). For more information, refer to the following user guides:

 

IP User Guides

Intel® Agilex Devices

    R-Tile IP User Guides

    P-Tile IP User Guides

Intel® Stratix® 10 Devices

    P-Tile User Guides

    H-Tile/L-Tile User Guides

Intel® Arria® 10 and Intel® Cyclone® 10 Devices User Guides

 

Design Example User Guides

Intel® Agilex Devices

    R-Tile Design Example User Guides

    P-Tile Design Example User Guides

Intel® Stratix® 10 Devices

    P-Tile Design Example User Guides

    L/H-Tile Design Example User Guides

Intel® Arria® 10 and Intel® Cyclone® 10 Devices

 

IP Release Notes

Intel® Agilex Devices

Intel® Stratix® 10 Devices

Intel® Arria® 10 and Intel® Cyclone® 10 Devices

 

PHY Interface for PCI Express (PIPE) Using the Intel Transceiver Native PHY IP Core

You can also implement just the physical layer of PCIe using the Transceiver Native PHY IP core and stitch it together with the remaining protocol layers implemented as soft logic in the FPGA fabric. This soft logic can be your own design or a third-party IP.

Find out more about the Transceiver Native PHY IP core in the PIPE chapter of the following user guides:

Intel Stratix 10 Devices

Intel Arria 10 Devices

Intel Cyclone 10 Devices

Title Description
Intel® Arria® 10 Device Configuration via Protocol (CvP) Learn how to configure your Intel Arria 10 device using the PCIe protocol.
PCIe Avalon®-MM Master DMA Reference Design in Intel Arria 10 Device (Part 1) Learn how to set up the PCIe Avalon® Memory Mapped (Avalon-MM) DMA reference design hardware in Intel Arria 10 devices for both the Linux and Windows operating systems from this Part 1 video.
PCIe Avalon-MM Master DMA Reference Design in Intel Arria 10 Device (Part 2) Learn how to set up the PCIe Avalon Memort Mapped Master DMA reference design hardware in Intel Arria 10 devices for both the Linux and Windows operating systems from this Part 2 video.

Other Technologies

Intel, Quartus, Stratix, Cyclone and Arria are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries.

OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos.