Due to a problem in the Intel® Quartus® Prime Pro Edition software versions 20.1 and later, you may see hardware failures when using the Intel® Stratix® 10 10GBASE-KR PHY IP core.
This problem is because of incorrect timing constraints in the auto generated Intel® Stratix® 10 10GBASE-KR PHY IP core Synopsys Design Constraint (SDC) file. The paths to the xgmii_tx_dc input of the IP or from the xgmii_rx_dc output of the IP may be incorrectly constrained. This problem may occur even if no timing violations are reported in the Timing Analyzer.
Only IP implementations with the following clocking topologies are impacted by this problem:
• The xgmii_tx_clk port of the IP and the clock feeding the logic/MAC driving the xgmii_tx_dc port of the IP are both connected to the same externally-generated clock.
• The xgmii_rx_clk port of the IP and the clock feeding the logic fed by the xgmii_rx_dc port of the IP are both connected to the same externally-generated clock.
If your design uses the clocking topology listed above and is still in development, see the Workaround/Fix section below for corrective action. For designs already in production that use the clocking topology listed above, follow the steps below to see if any timing violations exist for a precompiled design.
- Locate the original auto generated 10GBASE-KR PHY sdc file: \\altera_xcvr_10gkr_s10_\synth\altera_xcvr_10gkr_s10_.sdc
- Rename this file to:\\altera_xcvr_10gkr_s10_\synth\altera_xcvr_10gkr_s10__original.sdc
- Copy the corrected-krphy-sdc-to-rename.sdc file at the following link (corrected-krphy-sdc-to-rename.sdc) into the same location and then rename it to the same name as the original sdc file(the "altera_xcvr_10gkr_s10_.sdc" name prior to the modification in step 2.
- Rerun the timing analysis for the project and check for violations.
**Note that the auto generated sdc file will be overwritten if the IP is regenerated so these steps will need to be repeated if the IP is regenerated.