Device Family: Intel® Stratix® 10

Intel Software: Quartus Prime Pro

Type: Answers

Area: Tools



Is the Intel® Stratix® 10 timing model correct in the Intel® Quartus® Prime Pro Edition software versions 18.0 Update 1 and 18.1?

Description

No, the Intel® Stratix® 10 timing model in the Intel® Quartus® Prime Pro Edition software version 18.0 Update 1 and 18.1 has a small miscorrelation. This is corrected in the Intel Quartus Prime Pro Edition software version 18.1 Update 1.

These design scenarios may be affected:

  • Designs that use source synchronous clocking
  • Designs with transfers between the reference clock and the output clock for IOPLLs
  • Designs with transfers between output clocks from different IOPLLs with different reference clocks

Almost all designs will see timing delays change but most transfers will be unaffected because of either Common Clock Pessimism Removal (CCPR) or the transfer being asynchronous.

Workaround/Fix

All Intel Stratix 10 designs should be reanalyzed for timing in the Intel Quartus Prime Pro Edition software version 18.1 Update 1 or a patched version of 18.0 Update 1 or 18.1.

Download and install Patch 1.45 for 18.0 Update 1 from the appropriate link below.

Download and install Patch 0.31 for 18.1 from the appropriate link below.

For designs that are already in production:

    1. Download and run the script lut8_iobuf_qsh_v3.tcl to check if the compiled design is affected by this problem. 

Command -> quartus_sh -t lut8_iobuf_qsh_v3.tcl -project <project name> -revision <revision name> -npaths 100 -debug 0 -verbose -check_lutmasks -vo_file simulation/modelsim/<revision name>.vo

Output -> lut8check.rpt, iobuf.rpt, paths.csv

iobuf.rpt and paths.csv report the paths that are affected by the timing model change

    2. If there are no paths identified as impacted, no action is needed.

    3. If there are paths identified as impacted and using the Intel Quartus Prime Pro Edition software version 18.1 or earlier, rerun timing analysis using the patched version of the Intel Quartus Prime Pro Edition software version 18.0 Update 1  or 18.1

        a.       If there is not sufficient margin then recompile the design. 
        b.      If there is sufficient margin, you may choose to perform no action
 
Steps to rerun timing analysis:
        1.    Download and install patch 1.45 for 18.0.1 or patch 0.31 for 18.1
        2.    Open the design using the patched version of the Intel Quartus Prime Pro Edition software
        3.    Go to Tools -> Timing Analyzer and open Timing Analyzer.
        4.    Run the following commands:
            a.       create_timing_netlist -model slow -force_dat
            b.       read_sdc
            c.       update_timing_netlist
 
lut8check.rpt reports the LUTs impacted by the problem described in KDB Why do I have functional errors in my Intel® Stratix® 10 design? If this report contains "Found 0 LUTs with potentially incorrect bit settings" then the compiled design is safe. If the design is affected then the LUTs with this problem will be listed in the report.