When instantiating a IP Compiler for PCI Express® core within Qsys, the following warnings can appear, even though the core is configured and connected correctly:
Warning: System.pcie_hard_ip_0.pcie_hard_ip_0: Module dependency loop involving: com.altera.sopcmodel.components.tclmodule.LiveModule "pcie_internal_hip"
Warning: System.pcie_hard_ip_0.pcie_hard_ip_0: Module dependency loop involving: com.altera.sopcmodel.components.tclmodule.LiveModule "avalon_clk", com.altera.sopcmodel.components.tclmodule.LiveModule "pcie_internal_hip"
Warning: System.pcie_hard_ip_0.pcie_internal_hip: pcie_internal_hip.pcie_core_clk cannot be both connected and exported
Warning: System.pcie_hard_ip_0.pcie_internal_hip: pcie_internal_hip.rc_rx_analogreset must be exported, or connected to a matching conduit.
These warnings are safe for the user to ignore. This issue will be addressed in a future release of the Qsys tool.