Why can't I observe any activity on the Triple Speed Ethernet MegaCore Function’s RGMII_OUT signals in the SignalTap II Logic Analyzer?

Device Family: Intel® Arria® 10 GT

Device Family: Intel® Arria® 10 GX

Device Family: Intel® Arria® 10 SX

Device Family: Arria® II GX

Device Family: Arria® II GZ

Device Family: Arria® V GT

Device Family: Arria® V GX

Device Family: Arria® V GZ

Device Family: Arria® V ST

Device Family: Arria® GX

Device Family: Cyclone® II

Device Family: Cyclone® III

Device Family: Cyclone® III LS

Device Family: Cyclone® IV E

Device Family: Cyclone® IV GX

Device Family: Cyclone® V E

Device Family: Cyclone® V GT

Device Family: Cyclone® V GX

Device Family: Cyclone® V SE

Device Family: Cyclone® V ST

Device Family: Cyclone® V SX

Device Family: Intel® Stratix® 10 GX

Device Family: Intel® Stratix® 10 SX

Device Family: Stratix® II

Device Family: Stratix® II GX

Device Family: Stratix® III

Device Family: Stratix® IV E

Device Family: Stratix® IV GT

Device Family: Stratix® V E

Device Family: Stratix® V GS

Device Family: Stratix® V GT

Device Family: Stratix® V GX

Type: Answers

Area: Intellectual Property

The RGMII_OUT registers are implemented using Alt DDIO_OUT atoms which cannot be observed using SignalTap as a routing path to the core is not possible. Hence it is not possible to signaltap these nodes.

In the SignalTap II Logic Analyzer, the RGMII_OUT signals are only visible by selecting SignalTap II: pre-synthesis as filter, however after compilation, from the Compilation Report > Analysis & Synthesis > In-System Debugging, you will find that the status of the RGMII_OUT signals are illegal and these signals are connected to GND.

If you change SignalTap IIs filter to SignalTap II: post-fit, you are unable to find the RGMII_OUT signals.

Why can't I observe any activity on the Triple Speed Ethernet MegaCore Function s RGMII_OUT signals in the SignalTap II Logic Analyzer?

Description

Workaround/Fix