Device Family: Intel® Agilex™

Intel Software: Quartus Prime Pro

Type: Answers

Area: Component


Last Modified: December 14, 2020
Version Found: v20.1
Version Fixed: v20.4
Bug ID: 22011712537

Why is the nINIT_DONE signal always stuck in a HIGH state when using the Reset Release Intel® FPGA IP in Intel® Agilex™ devices?

Description

Due to a problem with the Reset Release Intel® FPGA IP in Intel® Quartus® Prime Pro Edition software version 20.3 and earlier, the nINIT_DONE signal is always stuck in a HIGH state when using Intel® Agilex™ devices.

Workaround/Fix

To fix this issue, recompile the design in Intel® Quartus® Prime Pro Edition software starting from version 20.4.

In Intel® Quartus® Prime Pro Edition software version 20.4, Intel® Quartus® Prime will allow the SOF generated from version 20.3 and below to program into Intel® Agilex™. However, Intel® Quartus® Prime Pro Edition software will report critical warning message as shown below if you try to program the SOF generated from version 20.3 and below through command line. The following critical warning message will not be reported if using Intel® Quartus® Prime Programmer.

Critical Warning: The SOF provided is generated using Intel® Quartus® Prime Pro Edition software version 20.3 and below. Kindly recompile the design on Intel® Quartus® Prime Pro Edition software version 20.4 and above. Using SOF generated in Intel® Quartus® Prime Pro Edition software version 20.4 and above will cause the output of the Reset Release Intel® FPGA IP to behave abnormally.