The Quartus® Prime software incremental compilation feature is the most productive incremental design methodology for high-density FPGAs. It reduces compilation times by up to 70 percent while preserving the results of unchanged logic in your design.
To search for known incremental compilation issues and technical support solutions, use Intel's Knowledge Database. You can also visit the Intel Community site to discuss technical issues with other Intel users.
For further technical support, use mySupport to create, view, and update service requests.
Incremental compilation resources
Table 1 provides links to available documentation on incremental compilation.
This user guide describes block-based design flows, also known as modular or hierarchical design flows. These advanced flows enable the preservation of design blocks (or logic comprising a hierarchical design instance) within a project, and reuse of design blocks in other projects.
Table 2 provides links to available training and demonstrations on incremental compilation.
Table 2. Incremental Compilation Training and Demonstrations