Design Space Explorer (DSE) Design Example

Design Space Explorer II (DSE) is a simple and easy-to-use design optimization utility that leverages a new exploration engine. DSE II is included with the Quartus® II software v14.1 and later. DSE II explores and reports the results of your optimization focus for a design. You can target design performance, area utilization, or power dissipation improvements.

DSE II uses predefined Quartus II compiler settings that make it easy to determine the optimal settings for a particular design.

The following lists the objectives of this design example:

  • Run a default Quartus II compilation flow on a design example
  • Run a DSE II exploration flow on a design example
  • Learn how the DSE II GUI and exploration options can help you find the optimal settings for your design

This example was developed using the Quartus II software v14.1 running on a PC. This archived design example has an OpenCore Ethernet media access control (MAC) instance targeted to a Stratix® V device. The core is constrained within a LogicLockTM region in the selected device.

Default Compilation

To run the default compilation, perform the following steps:

  1. Download the MAC_top.qar project archive file and save it to your computer.
  2. Start Quartus II GUI and un-archive the design. To restore the archived project, from the Project menu, click Restore Archived Project, and point to the archive file location.
  3. Use the default directory name prompted in the dialog box, and click OK.
  4. To compile the project with default settings, from the Processing menu, click on the Start Compilation  icon on the Quartus II GUI to compile the design. The compilation takes a few minutes to complete.
  5. After the compilation completes, from the Processing menu, click Compilation Report to open the Compilation Report panel.
  6. Click on the + sign next to the TimeQuest Timing Analyzer report section under the compilation report to view the timing failures. You will see that the design has setup and hold violations on the Clk_regRx_clk andClk_125M domains. Figure 1 shows a screenshot of the report from the Multicorner Timing Analysis Summary.

You will notice that these compilation results do not meet timing. With DSE II, this compilation acts as your base compilation. You can set an exploration focus in DSE II, which will target an optimization goal. DSE II will then compile several exploration points and summarize the achieved gains based on the optimization goal that you chose.

Run a DSE II Exploration

To run a DSE II exploration that determines the best settings for this design, perform the following steps:

  1. From the Tools menu of the Quartus II software GUI, click Launch Design Space Explorer II. Click Yes when prompted. This opens another instance of the project in DSE II.
  2. Select Design exploration under Compilation. Optionally, you can rename the exploration in the Name text field (eg: dse1).
  3. Expand Exploration Settings, and select your exploration focus from the Explore for drop-down menu.

    Figure 2. Exploration Settings

  4. In this design example, we focus on closing timing. Select Timing (High Effort), and set the number of seeds to 5.

    Figure 3. Setting the Timing

  5. Start exploring the design with DSE II, by clicking on the Start    icon on the DSE II GUI. By default, the results of the DSE II explorations are saved in the project directory named dse.
  6. You can check the status of each exploration point under the Status tab.

    Figure 4. Status Tab

    The compilation time for the DSE II explorations depends on the compute resources available on your machine. You can run explorations on a compute farm with the DSE II to reduce compilation time.


  7. After compiling all the exploration points, you can view a summary of all the exploration points in a tabular form. Exploration points 1, 2, 4, and 5 have met timing closure.

    Figure 5. Summary of Exploration Points

    You can use the best timing-focused exploration point by selecting the respective archive folder in the design directory.

Design Examples Disclaimer

These design examples may only be used within Intel Corporation devices and remain the property of Intel. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Intel expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Intel.