Intel Agilex® 7 Hard Processor System Technical Reference Manual

ID 683567
Date 1/11/2024
Public
Document Table of Contents

1. Intel Agilex® 7 Hard Processor System Technical Reference Manual Revision History

Updated for:
Intel® Quartus® Prime Design Suite 23.1
Table 1.   Intel Agilex® 7 Hard Processor System Technical Reference Manual Revision History Summary
Chapter Date of Last Update
Introduction to the Hard Processor System August 16, 2023
Cortex*-A53 MPCore Processor September 19, 2023
Cache Coherency Unit August 16, 2023
System Memory Management Unit August 16, 2023
System Interconnect August 16, 2023
HPS-FPGA Bridges August 16, 2023
DMA Controller August 16, 2023
On-Chip RAM August 16, 2023
Error Checking and Correction Controller August 16, 2023
Clock Manager September 19, 2023
Reset Manager September 19, 2023
System Manager August 16, 2023
Hard Processor Subsystem I/O Pin Multiplexing August 16, 2023
NAND Flash Controller September 19, 2023
SD/MMC Controller January 11, 2024
Ethernet Media Access Controller August 16, 2023
USB 2.0 OTG Controller August 16, 2023
SPI Controller August 16, 2023
I2C Controller August 16, 2023
UART Controller August 16, 2023
General-Purpose I/O Interface August 16, 2023
Timer August 16, 2023
Watchdog Timer August 16, 2023
CoreSight* Debug and Trace August 16, 2023
Booting and Configuration April 10, 2023
Accessing the SDM Quad SPI Flash Controller through HPS August 16, 2023
Operational Status of the HPS to the FPGA Logic January 11, 2024
Table 2.  Introduction to the Hard Processor System Revision History
Document Version Changes
2023.08.16 Updated the links to the HTML and Zip files in the Address Map and Register Descriptions section.
2023.04.10 Updated product family name to " Intel Agilex® 7".
2022.08.22 Made the following changes:
  • Removed RGMII because it does not support FPGA I/O
2021.07.06 Updated the AXI* bridge naming to match the Intel® Quartus® Prime software.
2019.09.30 Added links to access the complete HPS address map and register definitions.
2019.04.02 Initial release.
Introduction to the Hard Processor System
Table 3.   Cortex*-A53 MPCore Processor Revision History
Document Version Changes
2023.09.19 Made the following updates:
  • Updated the reset sequence for all cores in the Bringing the Cortex* -A53 MPCore out of Reset section.
2023.08.16 Updated the links to the HTML and Zip files in the Address Map and Register Descriptions section.
2023.04.10 Updated product family name to " Intel Agilex® 7".
2021.11.12 Corrected the numbering for the FPGA to HPS interrupt numbers in the GIC Interrupt Map table.
2019.09.30 Added links to access the complete HPS address map and register definitions.
2019.04.02 Initial release.
Cortex-A53 MPCore Processor
Table 4.  Cache Coherency Unit Revision History
Document Version Changes
2023.08.16 Updated the links to the HTML and Zip files in the Address Map and Register Descriptions section.
2023.04.10 Updated product family name to " Intel Agilex® 7".
2021.07.06 Updated the AXI* bridge naming to match the Intel® Quartus® Prime software.
2019.09.30 Added links to access the complete HPS address map and register definitions.
2019.07.01 Added the following sections:
  • Reset and Initialization
  • Discovery Routine
  • Operational State
  • Maintenance Operations
  • Error Handling
  • OCRAM Firewall
2019.04.02 Initial release.
Cache Coherency Unit
Table 5.  System Memory Management Unit Revision History
Document Version Changes
2023.08.16 Updated the links to the HTML and Zip files in the Address Map and Register Descriptions section.
2023.04.10 Updated product family name to " Intel Agilex® 7".
2021.07.06 Updated the AXI* bridge naming to match the Intel® Quartus® Prime software.
2019.09.30 Added links to access the complete HPS address map and register definitions.
2019.04.02 Initial release.
System Memory Management Unit
Table 6.  System Interconnect Revision History
Document Version Changes
2023.08.16 Updated the links to the HTML and Zip files in the Address Map and Register Descriptions section.
2023.04.10 Updated product family name to " Intel Agilex® 7".
2022.11.11 Updated section: Example (Recommended) System Memory Mapping Scheme by removing incorrect information
2022.08.22 Added new section: Example (Recommended) System Memory Mapping Scheme
2021.07.06 Updated the AXI* bridge naming to match the Intel® Quartus® Prime software.
2021.02.23 Changed the "self-refresh" information in SDRAM L3 Interconnect Resets
2019.09.30 Added links to access the complete HPS address map and register definitions.
2019.07.01
  • Added the missing data width for MPFE blocks in Figure: Block Diagram.
  • Corrected the Figure: Generic Timestamp Connection.
  • Corrected the GIC address region in Figure: L3 Address Regions.
  • Corrected the address range in Figure: SDRAM Regions.
  • Added a new section: Peripheral Region Address Map.
2019.04.02 Initial release.
System Interconnect
Table 7.   HPS-FPGA Bridges Revision History
Document Version Changes
2023.08.16 Updated the links to the HTML and Zip files in the Address Map and Register Descriptions section.
2023.04.10 Updated product family name to " Intel Agilex® 7".
2022.11.11 Added the max frequency value for the "Clock domain" property for these tables:
  • FPGA-to-HPS Bridge Properties
  • HPS-to-FPGA Bridge Properties
  • Lightweight HPS-to-FPGA Bridge Properties
2022.08.22 Added AxPROT[2:0] considerations and FPGA-to-HPS Example Transactions
2021.07.06
  • Added "Shareable Domain" information by adding the following chapters:
    • F2H and F2SDRAM Restrictions
    • FPGA-to-SDRAM Example Transactions
    • FPGA-to-HPS Example Transactions
  • Updated the AXI* bridge naming to match the Intel® Quartus® Prime software.
2021.02.23
  • Added MPFE Switch information by adding the following sections:
    • FPGA-to-HPS and MPFE Switch
    • FPGA-to-HPS Fabric Bypass Mux
  • Fixed "Figure 20: Interface Destination Selection Tab" in the FPGA-to-HPS MPFE Switch
2019.09.30 Added links to access the complete HPS address map and register definitions.
2019.07.01 Added information about FPGA Fabric Bypass Mux in section: FPGA-to-HPS Bridge.
2019.04.02 Initial release.
Bridges
Table 8.  DMA Controller Revision History
Document Version Changes
2023.08.16 Updated the links to the HTML and Zip files in the Address Map and Register Descriptions section.
2023.04.10 Updated product family name to " Intel Agilex® 7".
2020.01.25 Clarified reset information in section: DMA Controller Block Diagram.
2019.09.30 Added links to access the complete HPS address map and register definitions.
2019.04.02 Initial release.
DMA Controller
Table 9.  On-Chip RAM Revision History
Document Version Changes
2023.08.16 Updated the links to the HTML and Zip files in the Address Map and Register Descriptions section.
2023.04.10 Updated product family name to " Intel Agilex® 7".
2019.09.30 Added links to access the complete HPS address map and register definitions.
2019.04.02 Initial release.
On-Chip RAM
Table 10.  Error Checking and Correction Controller Revision History
Document Version Changes
2023.08.16 Updated the links to the HTML and Zip files in the Address Map and Register Descriptions section.
2023.04.10 Updated product family name to " Intel Agilex® 7".
2019.09.30 Added links to access the complete HPS address map and register definitions.
2019.04.02 Initial release.
Error Checking and Correction Controller
Table 11.  Clock Manager Revision History
Document Version Changes
2023.09.19 Made the following updates:
  • Corrected the Figure: Clock Manager Block Diagram.
2023.08.16 Updated the links to the HTML and Zip files in the Address Map and Register Descriptions section.
2023.04.10 Updated product family name to " Intel Agilex® 7".
2021.07.06 Updated the AXI* bridge naming to match the Intel® Quartus® Prime software.
2019.09.30 Added links to access the complete HPS address map and register definitions.
2019.04.02 Initial release.
Clock Manager
Table 12.  Reset Manager Revision History
Document Version Changes
2023.09.19 Updated the following sections regarding "Reset Sequences" and Preserving SDRAM contents":
  • Warm Reset Sequence
  • Watchdog Reset Sequence
  • Preserving SDRAM Contents
2023.08.16 Updated the links to the HTML and Zip files in the Address Map and Register Descriptions section.
2023.04.10 Made the following changes:
  • Added new topic: Preserving SDRAM Contents
  • Updated product family name to " Intel Agilex® 7".
2023.01.19 Added the HPS_COLD_nRESET Pin Function section
2021.07.06 Updated the AXI* bridge naming to match the Intel® Quartus® Prime software.
2021.03.09 Updated information about HPS_COLD_nRESET in Reset Manager.
2021.02.23 Changed the "self-refresh" information in:
  • Reset Handshaking
  • Warm Reset Sequence
2020.07.30 Corrected the following signal callouts:
  • s2f_cold_rst_n to s2f_cold_rst
  • s2f_rst_n to s2f_rst
  • s2f_watchdog_rst_n to s2f_watchdog_rst
2020.06.30 Added a clarification note under HPS Reset Domains.
2020.01.25 Added a new section: HPS-to-FPGA Reset Sequence.
2019.09.30 Added links to access the complete HPS address map and register definitions.
2019.07.01 Corrected steps in section: Warm Reset Sequence.
2019.04.02 Initial release.
Reset Manager
Table 13.  System Manager Revision History
Document Version Changes
2023.08.16 Updated the links to the HTML and Zip files in the Address Map and Register Descriptions section.
2023.04.10 Updated product family name to " Intel Agilex® 7".
2021.09.28
  • Added information about GPI and GPO (HPS-FPGA gpio) in the System Manager and System Manager Block Diagram.
  • Added the GPIO interconnect between HPS and FPGA section.
2019.09.30 Added links to access the complete HPS address map and register definitions.
2019.04.02 Initial release.
System Manager
Table 14.  Hard Processor System I/O Pin Multiplexing Revision History
Document Version Changes
2023.08.16 Updated the links to the HTML and Zip files in the Address Map and Register Descriptions section.
2023.04.10 Updated product family name to " Intel Agilex® 7".
2023.02.14 Minor updates specific to the Intel Agilex device family. Removed mention of Platform Designer.
2022.05.13 Corrected the Programmable I/O Timing Characteristics link in the Intel Agilex Dedicated Configuration Registers to point to the Intel Agilex Dedicated Configuration Registers web page.
2021.09.10 Removed mention of device tree for Platform Designer handoff.
2021.08.04 Updated the link in the Features of the HPS I/O Block section to point to the External Memory Interfaces Intel Agilex FPGA IP User Guide.
2019.09.30 Added links to access the complete HPS address map and register definitions.
2019.04.02 Initial release.
Hard Processor System I/O Pin Multiplexing
Table 15.  NAND Flash Controller Revision History
Document Version Changes
2023.09.19 Added a note regarding boot and performance modes in the Timing Registers chapter.
2023.08.16 Updated the links to the HTML and Zip files in the Address Map and Register Descriptions section.
2023.04.10 Made the following updates:
  • Updated recommended tie-off value for the NAND_ALE and NAND_CLE signals in the NAND Flash Controller Interface Signals (Routed to HPS I/O) table.
  • Updated recommended tie-off value for the nand_ale_o and nand_cle_o signals in the NAND Flash Controller Interface Signals (Routed to FPGA I/O) table.
  • Updated product family name to " Intel Agilex® 7".
2022.11.11 Made the following updates:
  • Added complete Signal Interface tables with default and tie off values in section: NAND Flash Controller Signal Description
  • Updated to state that spare area is not ECC protected
2020.01.25 Clarified reset information in section: Taking the NAND Flash Controller Out of Reset.
2019.09.30 Added links to access the complete HPS address map and register definitions.
2019.04.02 Initial release.
NAND Flash Controller
Table 16.  SD/MMC Controller Revision History
Document Version Changes
2024.01.11 Removed the Device Support section.
2023.08.16 Updated the links to the HTML and Zip files in the Address Map and Register Descriptions section.
2023.04.10 Updated product family name to " Intel Agilex® 7".
2022.11.11 Added complete Signal Interface tables with default and tie off values in section: SD/MMC Controller Signal Description
2021.07.06 Added the "SD/MMC Controller Signal Description" table to the SD/MMC Controller Signal Description.
2020.01.25 Clarified reset information in section: Taking the SD/MMC Controller Out of Reset.
2019.09.30 Added links to access the complete HPS address map and register definitions.
2019.04.02 Initial release.
SD/MMC Controller
Table 17.  Ethernet Media Access Controller Revision History
Document Version Changes
2023.08.16 Updated the links to the HTML and Zip files in the Address Map and Register Descriptions section.
2023.04.10 Updated product family name to " Intel Agilex® 7".
2023.01.25 Added link to the GSRD for Agilex F-Series Transceiver SoC development kit.
2022.11.11 Added complete Signal Interface tables with default and tie off values in the following sections:
  • EMAC Controller I/O Signals
  • FPGA Routing
  • MDIO Interface
  • Timestamp Interface Controller Signal Description
2022.08.22 Made the following changes:
  • Removed RGMII because it does not support FPGA I/O
2021.08.04 Updated the following figures:
  • EMAC System Integration
  • EMAC to FPGA Routing Example
  • EMAC Clock Domains
  • EMAC Block Diagram
2021.04.09 Added emac_clk_tx_i handling requirement for exported HPS EMAC GMII interface in the EMAC FPGA Interface Initialization section.
2020.11.11 Corrected the values for port name emac_phy_txclk_o in Table: PHY Interface Options.
2020.08.18 Updated EMAC HPS Interface Initialization to clarify how to verify RX PHY clocks after bringing the Ethernet PHY out of reset.
2019.09.30 Added links to access the complete HPS address map and register definitions.
2019.04.02 Initial release.
Ethernet Media Access Controller
Table 18.  USB 2.0 OTG Controller Revision History
Document Version Changes
2023.08.16 Updated the links to the HTML and Zip files in the Address Map and Register Descriptions section.
2023.04.10 Updated product family name to " Intel Agilex® 7".
2022.11.11 Added complete Signal Interface tables with default and tie off values in section: USB 2.0 ULPI PHY Signal Description
2020.01.25 Clarified reset information in section: Taking the USB 2.0 OTG Controller Out of Reset.
2019.09.30 Added links to access the complete HPS address map and register definitions.
2019.04.02 Initial release.
USB 2.0 OTG Controller
Table 19.  SPI Controller Revision History
Document Version Changes
2023.08.16 Updated the links to the HTML and Zip files in the Address Map and Register Descriptions section.
2023.04.10 Updated product family name to " Intel Agilex® 7".
2022.11.11 Added complete Signal Interface tables with default and tie off values in sections: Interface to HPS I/O and FPGA Routing
2021.07.06 Removed "Loan I/O" information from SPI Slave
2019.09.30 Added links to access the complete HPS address map and register definitions.
2019.04.02 Initial release.
SPI Controller
Table 20.  I2C Controller Revision History
Document Version Changes
2023.08.16 Updated the links to the HTML and Zip files in the Address Map and Register Descriptions section.
2023.04.10 Updated product family name to " Intel Agilex® 7".
2022.11.11 Added complete Signal Interface tables with default and tie off values in section: I2C Controller Signal Description
2019.09.30 Added links to access the complete HPS address map and register definitions.
2019.04.02 Initial release.
I2C Controller
Table 21.  UART Controller Revision History
Document Version Changes
2023.08.16 Updated the links to the HTML and Zip files in the Address Map and Register Descriptions section.
2023.04.10 Updated product family name to " Intel Agilex® 7".
2022.11.11 Added complete Signal Interface tables with default and tie off values in section: UART Controller Signal Description
2019.09.30 Added links to access the complete HPS address map and register definitions.
2019.04.02 Initial release.
UART Controller
Table 22.  General-Purpose I/O Revision History
Document Version Changes
2023.08.16 Updated the links to the HTML and Zip files in the Address Map and Register Descriptions section.
2023.04.10 Updated product family name to " Intel Agilex® 7".
2022.11.11 Added new section: General-Purpose I/O Signal Description containing complete Signal Interface tables with default and tie off values
2019.09.30 Added links to access the complete HPS address map and register definitions.
2019.04.02 Initial release.
General-Purpose I/O Interface
Table 23.  Timers Revision History
Document Version Changes
2023.08.16 Updated the links to the HTML and Zip files in the Address Map and Register Descriptions section.
2023.04.10 Updated product family name to " Intel Agilex® 7".
2019.09.30 Added links to access the complete HPS address map and register definitions.
2019.04.02 Initial release.
Timers
Table 24.  Watchdog Timers Revision History
Document Version Changes
2023.08.16 Updated the following sections:
  • Updated the definition of a timeout period in the Watchdog Timers Counter.
  • Updated the links to the HTML and Zip files in the Address Map and Register Descriptions section.
2023.04.10 Updated product family name to " Intel Agilex® 7".
2019.09.30 Added links to access the complete HPS address map and register definitions.
2019.04.02 Initial release.
Watchdog Timers
Table 25.  CoreSight Debug and Trace Revision History
Document Version Changes
2023.08.16 Updated the links to the HTML and Zip files in the Address Map and Register Descriptions section.
2023.04.10 Updated product family name to " Intel Agilex® 7".
2019.09.30 Added links to access the complete HPS address map and register definitions.
2019.04.02 Initial release.
CoreSight Debug and Trace
Table 26.  Booting and Configuration Revision History
Document Version Changes
2023.04.10 Updated product family name to " Intel Agilex® 7".
2022.11.11 Added link to the Intel Agilex SoC FPGA Boot User Guide
2021.03.09 Updated information about HPS_COLD_nRESET in Device Response to External Configuration and Reset Events.
2020.06.30 Added a new section: Device Response to External Configuration and Reset Events to clarify the nCONFIG operation.
2019.07.01 Simplified information in the appendix. For more information, refer to the Intel Agilex Configuration User Guide and Intel Agilex Boot User Guide.
2019.04.02 Initial release.
Booting and Configuration
Table 27.  Accessing the SDM Quad SPI Flash Controller through HPS Revision History
Document Version Changes
2023.08.16 Updated the links to the HTML and Zip files in the Address Map and Register Descriptions section.
2023.04.10 Updated product family name to " Intel Agilex® 7".
2019.09.30 Added links to access the complete HPS address map and register definitions.
2019.04.02 Initial release.
Accessing the Secure Device Manager Quad SPI Flash Controller through HPS
Table 28.  Operational Status of the HPS to the FPGA Logic Revision History
Document Version Changes
2024.01.11 Initial release.
Operational Status of the HPS to the FPGA Logic