Universal Serial Bus (USB*) Specifications

Universal Serial Bus 3.0

PHY Interface For the PCI Express* and USB 3.0 Architectures

File Type/Size: PDF 630KB

This document is a final version of the PIPE spec that supports PCI Express* and USB 3.0 architectures. The PIPE spec (PHY Interface for PCI Express* and USB 3.0 Architectures) describes a standardized interface between PCIe* Gen2 and USB 3.0 MAC implementations and PCIe* Gen2 and USB 3.0 PHY implementations. This document can be used for both discrete PHY parts and for PHYs that are foundry macrocell implementations.

eXtensible Host Controller Interface (XHCI) draft specification for USB, Revision 3.0
The eXtented Host Controller Interface (xHCI) draft specification describes the register-level host controller interface for Universal Serial Bus (USB) Revision 2.0 and above. The specification includes a description of the hardware/software interface between system software and the host controller hardware.

This specification is intended for hardware component designers, system builders and device driver (software) developers. The reader is expected to be familiar with the current Universal Serial Bus Specification revisions. Note: In case of conflicts between the xHCI and the USB specifications, the USB specifications take precedence and must be followed.

USB 2.0 specification (download from the USB-IF web site)
On-The-Go supplement to the USB 2.0 specification
USB 2.0 Transceiver Macrocell Interface (UTMI), 1.05

File Type/Size: PDF 415KB

The USB 2.0 Transceiver Macrocell Interface, version 1.05(UTMI) specification defines the USB 2.0 Transceiver Macrocell Interface (UTMI). The UTMI provides a standardized interface for USB transceivers that are used in devices. This is particularly useful when interfacing between the high-speed (480 MHz) USB 2.0 Transceiver and the Serial Interface Engine (SIE) which runs the USB 2.0 protocol for a device. The UTMI allows ASIC vendors and foundries to implement a compliant USB 2.0 Transceiver Macrocell and add it to their device libraries. Peripheral and IP vendors will be able to develop their designs to the UTMI, insulated from the high-speed and analog circuitry issues associated with the USB 2.0 interface, thus minimizing the time and risk of their development cycles.

USB 2.0 Transceiver and Macrocell Tester (T&MT) Interface specification

File Type/Size: PDF 90KB

The USB 2.0 Transceiver and Macrocell Tester (T&MT) Interface specification complements the UTMI specification by defining a mechanical and electrical interface for testing the macrocell. A daughter card form factor is defined, which will allow the interchange if UTMI compliant designs between testing and prototyping environments. The daughter card dimensions and placement of the interfacing connector are defined in this document. The connector pin assignment is described also, using the naming conventions of the USB 2.0 Universal Transceiver Macrocell Interface (UTMI) specification.

Universal Host Controller Interface (UHCI) Design Guide

File Type/Size: PDF 512KB

< br /> The Universal Host Controller Interface (UHCI) Design Guide describes a Universal Host Controller Interface (UHCI) for a device that implements a Universal Serial Bus (USB) Host Controller.

Enhanced Host Controller Interface (EHCI) draft specification for USB, Revision 1.0
The Enhanced Host Controller Interface (EHCI) specification for Universal Serial Bus, Revision 1.0 describes the register-level interface for a Host Controller for the Universal Serial Bus (USB) Revision 2.0. The specification includes a description of the hardware component designers, system builders and device driver (software) developers.

EHCI Test Specification 1.1

File Type/Size: PDF 1.03MB

An EHCI host controller implementation is measured for compliance to the EHCI specification via a standardized suite of compliance tests. The test assertions and definitions of the tests, including descriptions of algorithms and the pass/fail criteria are documented in the EHCI Test specification 1.1. This specification is targeted to host controller implementations designing to the 1.0 revision of the EHCI specification.

EHCI Compliance Testing Program
The EHCI Compliance Testing Program measures an EHCI controller implementation for conformance to the EHCI specification. The EHCI compliance testing evaluates the functionality of the EHCI Controller function of a USB 2.0 host controller. It does not evaluate the functionality of the USB companion controllers.

USB2 Compliance Test Device Functional Specification, Revision 1.0

File Type/Size: PDF 315KB

USB2 Compliance programs for the USBIF Hub Transaction Translator and the Enhanced Host Controller Interface (EHCI) use specific test devices that provide consistent and controllable behavior. The USB2 Compliance Test Device Functional specification, Revision 1.0 is the functional device interface specification for these test devices. This specification includes a detailed description of the device framework, commands and other operational requirements of a USB2 Compliance Test Device. EHCI controller developers and USB2 Hub Transaction Translator developers can use this specification to construct low, full, and high-speed devices to use with the Transaction Translator and EHCI compliance test suites.

USB2 Debug Device Functional Specification, Revision 0.90

File Type/Size: PDF 305KB

The USB2 Enhanced Host Controller Interface (EHCI) defines a Debug Port interface that provides a viable alternative for kernel debugging on legacy-free platforms. The USB2 Debug Device Functional specification provides a detailed description of the device framework, commands, and other operational requirements of a USB2 Debug Device.

High-Speed USB Platform Design Guidelines

File Type/Size: PDF 314KB

The High-Speed USB Platform Design Guidelines, Rev. 1.0 provides guidelines for integrating a discrete USB 2.0 host controller onto a four-layer desktop motherboard. The material covered can be broken into three main categories: board design guidelines, EMI/ESD guidelines and front panel USB guidelines. It also covers some background information on the routing experiments and testing performed to validate the feasibility of 480 megabits per second on an actual motherboard. Finally, it contains a design checklist that lists each design recommendation described in the document.

Understanding WDM Power Management

File Type/Size: PDF 71KB

The Understanding WDM Power Management v1.0 white paper provides an overview of power management in the WDM architecture and the necessary code required to implement minimal support.

USB 2.0 High-Speed Electrical Test Fixture Reference Design

File Type/Size: EXE 1.37MB

The USB 2.0 high-speed electrical test fixture reference design provides the files necessary to produce a high-speed USB electrical test fixture. These files include stackup requirements, fab drawing, mechanical drawing, primary silkscreen file, gerbers for each layer, aperture files, drill file, paste mask files, solder mask files, allegro board file, schematics, bill of materials and stuffing options.