Silicon R&D Pipeline

As feature sizes become smaller and circuits operate at higher speeds, the challenges of delivering more powerful and power-efficient processors increase. Active power, off-state leakage, variability in transistor behavior, and other tendencies of increasingly small devices must be addressed in order to continue delivering smaller, more-powerful, energy-efficient processors, and, higher-speed, higher-bandwidth interconnects. Intel has already implemented several measures to address issues such as leakage power and we are actively researching silicon technologies that will take our products to 32nm and beyond.

Intel is looking at a variety of technologies including high-k/metal gate, 3-D transistors, and III-V materials, even carbon nanotubes, and semiconductor nanowires as high-mobility materials for future high-speed and low-power transistor applications and future interconnect applications.

High-k and metal gate

To address the leakage problems that come with shrinking transistors, Intel has identified a new high-k material, to replace the transistor's silicon dioxide gate dielectric, and new metals to replace the polysilicon gate electrode of NMOS and PMOS transistors. These new materials, along with the right process recipe, reduce gate leakage to less than 4% of what it was for the previous process generation, while delivering record transistor performance.

3-D and III-V transistors

For further down the road, Intel is investigating 3-D transistors that have a gate that controls the flow of current from 3 sides, rather than the single-sided control of today's conventional planar transistors. Intel is also researching transistors whose channel is made of "III-V" compound semiconductors. All of these are aimed at continuing performance improvements while reducing power.

Packaging technologies

Intel researchers are addressing the challenge of packing thinner, lighter and increasingly feature-rich functionality into less space through advanced packaging-related research and development activities.

Post CMOS

Silicon scaling in accordance with Moore's Law is expected to continue until at least 2020, but eventually alternative computing technologies are expected to be developed. Read about some of the technologies being investigated, all of which could eventually be heterogeneously integrated onto a silicon substrate.

International Technology Roadmap for Semiconductors

The International Technology Roadmap for Semiconductors is an assessment of the semiconductor industry's technology requirements with the objective of ensuring advancements in the performance of integrated circuits and remove roadblocks to the continuation of Moore's Law.