Developing the Silicon Future

As Intel's chip transistor counts rise in accordance with Moore's Law, each transistor is designed to be smaller and faster with the goal of increased microprocessor performance. The rising transistor count and their smaller size also means increased power consumption if nothing is done about it.

To meet this power challenge, Intel is exploring new ways to make high-speed and low-power transistors in the latter half of the next decade.

Improving current flow

Today's transistor channel is made of "doped" silicon, meaning it has some impurities. Intel is researching transistors and nanotechnology for future microprocessor applications including non-silicon materials called "III-V compound semiconductors," the III-V standing for their position on the periodic table. III-V materials in the transistor channel may allow the current to flow more easily, providing these benefits:

High-speed transistors operating at low supply voltage. Using non-silicon materials, these high-speed transistors could operate at 0.5 volts.
A dramatic reduction of voltage. High-performance microprocessors operate at approximately 1.0 volt today, but they could operate at around 0.5 volts with new channel material.

Plus, this compound semiconductor solution could be applicable to communications and optoelectronic circuits, which could potentially be integrated with complementary metal-oxide semiconductor (CMOS) logic on the same silicon chip.

Leveraging 40 years of silicon experience

Intel has integrated non-silicon materials into our current silicon process, including:

Silicon germanium (strained silicon)
Hafnium (high-k gate dielectrics)
Novel metals (gate electrodes)

Intel demonstrated the feasibility of III-V integration on silicon by producing a high-performance N-type III-V transistor on silicon shown at the International Electron Devices Meeting (IEDM) in December 2007.

Integrating III-V on a silicon substrate

For III-V compound semiconductors to become applicable for future high-speed and low-power digital applications, they must be integrated onto large silicon wafers, which avoids the difficulty, expense, and disruption of replacing our current mainstream silicon substrates.

In order to meet this goal, the work has been divided into three phases:

Material and device structure growth on silicon
Device integration and processing
Device measurement and analysis

Intel is working closely with universities on III-V research projects funded by Intel, and also forming partnerships with industry leaders, such as QinetiQ and IQE to help accelerate progress.

Phase 1: Material and device structure on silicon

The channel region between the source and drain must be formed on top of a grid structure of silicon called a lattice. The lattice spacing of III-V materials differs from that of silicon. When the atoms in the structure of each material get far apart, they can't connect due to lattice mismatch.

To avoid this, Intel and our partners have jointly developed graded, thin, non-silicon buffer layers that avoid defects while keeping the III-V channel intact. These buffer layers include gallium arsenide (GaAs) and indium aluminium arsenide (InAlAs), creating a III-V semiconductor composite metamorphic buffer structure on top of the silicon substrate. The metamorphic buffer filters out dislocations caused by the material mismatches, leaving a high-quality channel region.

To facilitate the integration with silicon CMOS, Intel has reduced the buffer thickness as much as possible, without impacting the overall material quality.

Phase 2: Device integration and processing

The transistors must be fabricated based on the buffer layers, so the next step is to develop the process for creating devices on the wafer. Our methods evolve with each experiment—for example, the contact resistance might be too great, and one way to reduce it might be to use different contact metals. In order to improve the contact resistance we might change the III-V source/ drain material by increasing indium concentration.

Phase 3: Device measurement and analysis

In the last step, all experimental transistors must be tested. For each, there is characterization, analysis, and theory. These results are charted against a baseline of theory, or expectations, to see where a particular device deviates. We can then determine the advantages of the new technology in relation to the old technology. To do so, we develop unique test structures to measure the effective velocity of electrons traveling through the transistor channel (mobility).

With nanometer-scale measurements, we can determine whether the better electron mobility in these new materials will result in some real transistor gain over current technologies.

Research progress being made

The research community is looking for ways to make III-V materials work because of the potential performance and power benefits, as well as the ability to integrate communications and optoelectronic circuits with CMOS logic on the same silicon chip. In the future, III-V devices and silicon CMOS transistors may coexist on the same silicon chip for increased performance and functionality with enhanced energy efficiency.

Although there are many difficult challenges to overcome, significant progress has been made by the research community. Always looking toward the future, Intel and our partners have recently demonstrated the world's first high-speed P-channel devices and expect to disclose their results at IEDM in December 2008.

"Although there are many difficult challenges to overcome, significant progress has been made by the research community and much excitement has been generated. Going forward, research on III-V-based transistors and their integration on large silicon wafers will be even more exciting and rewarding than ever," states Robert Chau, Intel senior fellow and director of transistor research and nanotechnology.

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