Page 2 of 8

Introduction

Gordon Moore first proposed the law that bears his name in the late '60's: chip complexity (as defined by the number of active elements on a single semiconductor chip) will double about every device generation, usually taken as about 18 calendar months [1]. This law has now been valid for more than three decades, and it appears likely to be valid for several more device generations, as shown in Figure 1.

The compelling desire of the semiconductor industry to follow Moore's Law has affected high-volume device manufacturing, driving both the cost per bit of the devices and the overall cost of the fabrication and assembly facilities needed to build them. (Additional effects such as those on the ramp rate towards high-volume manufacturing are also experienced, but these are not discussed in this paper.)

For Moore's Law to remain valid, feature size must continue to be reduced, but since this reduction is insufficient in and of itself, chip size must continue to increase. Together, these two trends have not only maintained Moore's Law, but have accounted for the phenomenal success of our industry, since the cost per device element has now decreased by several orders of magnitude! Compared to every other commodity in the world, semiconductor chips are cheap, and continue to get cheaper (on a per element basis) every year.

The reduction in cost per active chip element is shown in Figure 2. Notice that while this cost continues to decrease, there appears to be a break in the curve: one section follows early predictions of Moore's Law, and the other departs from these predictions. This will be discussed later.

Many programs are associated with following Moore's Law and each has consequences for the cost per chip element, as shown in Table 1.

Most of these programs tend to contribute to a reduction in chip element cost, but some of them, especially those dealing directly with increased chip and process complexity, tend to increase that cost. Fortunately, scaling, reduced feature size, improved yield, and increased wafer diameter more than make up for the added costs of more expensive packages and more complex processing.

Figure 3 shows the other major consequence of following Moore's Law. The reduction in cost per chip element is just offset by the increase in element density, leading to an essentially constant cost per individual chip. However, as a result, overall factory costs increase almost exponentially as we struggle to meet the ever increasing demand for more and larger high-performance chips. In order to meet cost per chip goals, cost per factory has increased to the point where high-volume factories now cost several billion dollars! So being successful in reducing chip costs brings its own share of additional problems. Building, equipping, and maintaining billion dollar factories tax even the most successful companies. This explosion of factory cost has come to be known as Moore's Second Law--one we do NOT wish to follow with such great zeal!

Many of the same programs that have driven cost per chip element down are also responsible for the trend shown in Figure 3. In addition, some operational programs that have had little direct influence on cost per chip element have significant influence on factory cost. These additional programs are shown in Table 2.

Tables 1 and 2 are combined, below, in Table 3, which shows two emerging problems with regard to both cost per chip element and factory cost containment:

1. Some goals of the programs are in conflict: lowering the cost per element actually adds to factory cost.
2. The leverage of some of the programs is diminishing: for example, we will not exceed 100% yield or 100% automation.

Hence, other means are necessary to meet cost projection goals for factories and chip elements.

The major program that does not suffer from topping out or from conflict is improving operational efficiency. However, before we discuss this, some additional forces acting on the manufacturing environment are discussed


    Page 2 of 8