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AUTHORS' BIOGRAPHIES

		Mirng-Ji Lii is a Packaging Design Integrator in the Assembly Technology Development group at Intel. He has various experience in microprocessor packaging technology development and interconnect development such as flip chip, tape-automated bonding, and fine pitch wire bonding. He holds two U.S. patents and has published several technical papers. Currently, he leads a package design team to develop a cost-effective, high-performance packaging technology for future-generation microprocessors. His e-mail address is mirng-ji.lii@intel.com.
		Bob Sankman is the manager of the Design and Integration group in Assembly Technology and Development at Intel. He has held various technical positions in his career at Intel including wafer fab process engineer, failure analysis engineer, Q & R lab manager, and microprocessor package design manager. Bob has a B.S.Ch.E. degree from the University of Illinois. His e-mail address is bob.sankman@intel.com.
		Hamid Azimi is currently the program manager for x60 substrate supplier certification in the Assembly Technology Development group at Intel. Hamid and his team work with Intel substrate suppliers to develop and certify a substrate material/process, which can meet cost, quality, reliability, and electrical performance targets. This includes substrates for mobile, DT, and server applications within the x60 generation. Hamid graduated with a Ph.D. degree in materials science from Leigh University in 1994 with expertise in fatigue and fracture of polymer composites and metals. He joined Intel in 1995 and since then has been working in the Assembly Technology Development group in the Material Technology Development Department for different platforms including PLGA, OLGA, FCPGA1 and, now, X60. His e-mail address is hamid.azimi@intel.com.
		Hwai-Peng Yeoh is an Integration and Substrate Development Manager in the Assembly Technology Development group in Intel, Malaysia. He has more than eight years of experience in advanced microprocessor packaging technology development that includes ceramic packaging for the P5 generation, dual cavity ceramic packaging for the P6 generation, Plastic Land Grid Array packaging, Multichip Module packaging for Itanium™ processor , and Flip-Chip Pin Grid Array packaging. He currently leads both integration and substrate development teams in FC-BGA1 packaging development for high-performance chipsets. His e-mail address is hp.yeoh@intel.com.
		Yuejin Guo has worked at Intel for years in the areas of assembly material development, new technology transfer, assembly process development, and assembly HVM production. His current position is as a Sr. Materials Engineer in the Assembly Technology Development group. Before joining Intel he was at Los Alamos National Lab as a researcher. Yuejin's technical interests are primarily in the area of packaging materials. He graduated from Caltech with a Ph.D. in chemistry. His e-mail address is yuejin.guo@intel.com.