MOS Scaling: Transistor Challenges for the 21st Century

MOS Scaling: Transistor Challenges for the 21st Century (continued)

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Authors' Biographies

Scott Thompson Scott Thompson
Scott Thompson joined Intel in 1992 after completing his Ph.D. under Professor C. T. Sah at the University of Florida on thin gate oxides. He has worked on transistor design and front-end process integration on Intel's 0.35, 0.25, and 0.18um silicon process technology design for the Pentium® and the Pentium® II microprocessors. Scott is currently managing the development of Intel's 0.13um transistor design. His email address is scott.thompson@intel.com.

Paul Packan Paul Packan
Paul Packan received his Ph.D. degree in Electrical Engineering in 1991 from Stanford University. He joined Siemens AG in Munich Germany in 1991 working in the area of high speed bipolar transistor architecture. In 1992 he joined Intel Corp. working in the field of process and device simulation for MOS devices. He worked on the development of the 0.35, 0.25, and 0.18um technologies and is currently managing the process and device modeling group. His email address is paul.a.packan@intel.com.

Mark T. Bohr Mark T. Bohr
Mark T. Bohr joined Intel in 1978 after receiving a MSEE from the University of Illinois. He has been a member of the Portland Technology Development group since 1978 and has been responsible for process integration and device design on a variety of DRAM, SRAM, and logic technologies, including recent 0.35um and 0.25um logic technologies. He is an Intel Fellow and director of process architecture and integration. He is currently directing development activities on 0.18um and 0.13um logic technologies. His email address is mark.bohr@intel.com.

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		Scott Thompson Scott Thompson joined Intel in 1992 after completing his Ph.D. under Professor C. T. Sah at the University of Florida on thin gate oxides. He has worked on transistor design and front-end process integration on Intel's 0.35, 0.25, and 0.18um silicon process technology design for the Pentium® and the Pentium® II microprocessors. Scott is currently managing the development of Intel's 0.13um transistor design. His email address is scott.thompson@intel.com.

		Paul Packan Paul Packan received his Ph.D. degree in Electrical Engineering in 1991 from Stanford University. He joined Siemens AG in Munich Germany in 1991 working in the area of high speed bipolar transistor architecture. In 1992 he joined Intel Corp. working in the field of process and device simulation for MOS devices. He worked on the development of the 0.35, 0.25, and 0.18um technologies and is currently managing the process and device modeling group. His email address is paul.a.packan@intel.com.

		Mark T. Bohr Mark T. Bohr joined Intel in 1978 after receiving a MSEE from the University of Illinois. He has been a member of the Portland Technology Development group since 1978 and has been responsible for process integration and device design on a variety of DRAM, SRAM, and logic technologies, including recent 0.35um and 0.25um logic technologies. He is an Intel Fellow and director of process architecture and integration. He is currently directing development activities on 0.18um and 0.13um logic technologies. His email address is mark.bohr@intel.com.