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Alternate Device Options

Many designers have proposed new device architectures to improve device and circuit performance. In this section, we evaluate three of the most widely explored options and discuss the potential advantages and disadvantages of each.

SOI Device

One technique proposed to improve CMOS performance is to fabricate the devices on a silicon on insulator (SOI) substrate. SOI devices are classified into two types depending on the extent of the channel depletion layer (partially depleted or fully depleted) compared to the silicon thickness (T_Si). Fully depleted devices are not practical for deep sub-micron devices since the silicon thickness needs to be ~10.0 nm to control short channel effects. This silicon thickness is extremely difficult to manufacture and causes large device external resistance due to shallow SDE depths. Partially depleted devices are more suitable for deep sub-micron devices. However, since the channel region of the silicon layer is not entirely channel depleted, a partially depleted device offers no advantage for short channel effects or channel length scaling.

Actually the partially depleted floating body can degrade short channel effects because of an uncontrolled lowering of V_T that is caused by impact ionization [28]. If the floating body can be controlled, partially depleted devices offer improvements in junction area capacitance, device body effect, and a gate-to-body coupling, which potentially results in a slightly larger drive current during switching.

Figure 42: Cross section of an SOI device

Table 3: Estimated improvement in circuit speed
by device feature for a SOI device with unconstrained I_OFF

The best case estimated impact of these parameters on current generation circuit speed improvements is shown in Table 3. We call it best case, since to date, no literature paper has demonstrated these device parasitic improvements without increasing the transistor off-state leakage. Studies done at Intel indicate that NMOS SOI devices require a somewhat higher threshold voltage than bulk devices to maintain an equivalent off-state leakage due to the floating body effect[28]. This higher threshold voltage offsets some of the other potential performance advantages of SOI. Also, in future high performance microprocessors where interconnect capacitances are becoming more dominant, the junction capacitance advantage of SOI will become less important. In summary, the performance gain going to the SOI architecture is less than one generation and will pose serious complications for circuit design due to floating body effects.

Si_1-xGe_x Channel Device

Another technique to improve transistor performance is to fabricate the device in a Si_1-xGe_x channel (see Figure 43). The Si_1-xGe_x channel region has been shown to increase hole mobility [29]. There are two reasons for the mobility gain: Si_1-xGe_x under compressive strain has improved mobility over Si; and the valence band offset between Si and Si_1-xGe_x localizes the hole inversion charge away from the SiO₂/Si interface, which reduces the effects of surface roughness scattering. Unfortunately, improving mobility becomes less important as the transistor is scaled into the deep sub-micron regime. This is due to the high lateral electric fields that cause the carrier velocity to saturate.

Figure 43: Cross section of a transistor fabricated with a
Si_1-xGe_x channel

In Figure 44, the ratio of saturated drive current to mobility change is plotted for different device sizes. For long channel device lengths, the improvement in drive current is equal to the improvement in mobility. However, for deep sub-micron devices with channel lengths of ~0.1um, a 4% improvement in mobility improves drive current by only 1%. If a Si_1-xGe_x channel improved electron or hole saturation velocity, there would be an improvement in drive current. Unfortunately, electron and hole saturation velocities are similar if not slightly lower in SiGe than they are in silicon.

Figure 44: Ratio of I_DSAT change to mobility change
versus channel length (for smaller devices, high electric
fields cause velocity saturation)

Dynamic V_T Device

For low supply voltage operation (<0.6 V), a dynamic threshold voltage MOS device (DTMOS) has been proposed [30,31]. A DTMOS is formed by connecting the gate to the well as shown in Figure 45. This connection causes the threshold voltage of the device to be lowered during switching thereby increasing the transistor drive current. This technique is limited to supply voltages less than 0.6V to prevent the forward bias well-to-source junction from conducting large forward bias diode currents. The DTMOS technique has been proposed for devices fabricated on either bulk silicon or SOI substrates. Fabrication of these devices on SOI substrates is easier due to the electrical isolation of both n- and p-wells.

Figure 45: Circuit schematic of a dynamic threshold
voltage MOS inverter

This technique can increase transistor drive current by over 20% through improved gate over drive (V_G-V_T). However, this technique offers little to no net gain over high performance, optimized, static V_T CMOS when differences in chip area are considered. When DTMOS is implemented on bulk silicon substrate (see Figure 46), there is a large performance degradation due to the increase in the switching load capacitance that is comprised of junction (C_J) and depletion (C_D) capacitance.

Figure 46: Transistor cross schematic of a dynamic
threshold voltage MOS inverter

The performance degradation from the junction and depletion capacitance can be significantly reduced for DTMOS fabricated on an SOI substrate. However, for DTMOS on SOI, the RC time constant associated with the well resistance (R_WELL) and depletion capacitance (C_D) is not compatible with high frequency microprocessor applications. The R_WELL*C_D time constant can be ~1ns, which would consume half of the clock period for today's 500 MHz microprocessors. To minimize the RC delay associated with the poly-Si gate, companies have added metals to reduce the resistance to 2-3W/sq. By comparison, a DTMOS device in SOI can easily have a resistance component (R_WELL) on the order of 10⁴-10⁵ W/sq. or greater.

Although each of these alternate device structures has certain advantages, the overall device improvement is relatively small. In addition, manufacturing costs and circuit issues make it extremely difficult to justify the adoption of any of these device architectures.

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