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Circuit and Device Interactions

The choice of power supply (V_CC) and threshold voltage (V_T) will be critical in determining whether the performance of 0.1um transistors can continue to be scaled. These parameters strongly affect chip active power, chip standby power, and transistor performance.

In this section, we review the power supply and threshold voltage scaling trends. We show that the loss in gate over drive (V_CC-V_T) is becoming so severe that this trend cannot continue without substantial loss in device performance. One possible solution that has been proposed is the use of dual threshold voltage transistors. It will be shown, however, that this will only extend the scaling trend by one technology generation at most.

V_CC and V_T Scaling

Figure 36 shows power supply and threshold voltage trends for Intel's microprocessor process technologies. As seen, the power supply is decreasing much more rapidly than threshold voltage. This has severe implications for device performance. Transistor drive current and therefore circuit performance is proportional to gate over drive (V_CC-V_T) raised to the power n where n is between 1 and 2 ((V_CC-V_T)ⁿ).

Figure 36: Power supply and threshold voltage scaling
trend

In Figure 36, the gate over drive is shown to be rapidly decreasing for deep sub-micron devices, thereby strongly degrading device performance. As discussed previously, aggressive oxide, SDE, and well engineering are used to overcome the loss in gate drive and maintain the historical rate of transistor improvement.

To understand why these power supply and threshold voltages are being chosen, we need to understand chip active and standby power trends. Active power is set by circuit switching and is defined as P = C_LOAD V_CC²f where f is the operating frequency and C_LOAD is the switching capacitance of the gate and wire load. Chip active power and frequency trends are shown for Intel's process technologies in Figure 37. Standby power results from junction and transistor sub-threshold source-to-drain leakage. For 0.1um transistors, the sub-threshold leakage is the dominant contributor to standby power.

Figure 37: Chip power and frequency trends for Intel's
process technologies

Figure 38: Off-state leakage versus channel length for
0.25um transistors with different threshold voltage

Sub-threshold leakage is fundamental to silicon MOSFET operation and is set by the device threshold voltage. Sub-threshold off-state leakage versus channel length characteristics is shown in Figure 38. The active and standby power trends for Intel's process technologies are shown in Figure 39. In this figure, several interesting points can be observed. First, as microprocessor complexity increases, chip power is increasing to ~10-20W. Second, standby power for 1um technology was .01% of active power, but is approaching 10% of active power in 0.1um technologies. In order to limit the increase of standby power, threshold voltages need to increase. However, this increase strongly affects device performance because of reduced gate over drive. To maintain acceptable leakage values, the V_T's of transistors will need to increase by >0.25 V.

Figure 39: Active and standby power trends for Intel's technologies

Dual V_T Architecture

If power supply and threshold voltage scaling continues at the current trend, further reduction in gate overdrive will occur. A general rule for high performance transistor design is to maintain a V_CC/V_T ratio of at least four. A ratio of four provides a gate swing of one V_T to turn the device off and three V_T to drive the device. Figure 40 plots the V_CC/V_T ratio for Intel's previous technologies as well as the current projected trend. The projected scaling trend shows that beyond the 0.25um technology, the ratio of V_CC/V_T will drop below 4. One technique to improve the gate drive and standby power trend is to offer circuit designers dual threshold voltage devices. This would consist of designing a high-performance, high-leakage, low-threshold voltage device and a low-performance, low-leakage, high-threshold voltage device. A chip would be designed such that only the critical paths would use the high-performance/high-leakage devices.

Figure 40: V_CC/V_T trend for Intel's process technologies

Figure 41 shows the performance and leakage current tradeoff for 0.25um technology, lower threshold voltage devices. A 100x increase in leakage current would be required to extend the present performance trend by one generation. Whether or not a 100x increase in leakage could be tolerated would depend heavily on the circuit architecture and power constraints of the chip.

Figure 41: Performance and leakage current tradeoff for
lower threshold voltage devices

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