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References
| [1] | Schnarch, Baruch, "PP/MT Scoreboarding: Turning the Low DPM Myth to Facts," Proceedings of the 1998 Intel Design and Test Technology Conference, pp. 13-18, Portland, OR, July 21-24, 1998. |
| [2] | Wayne Needham, internal memo based on data extracted from 1997 SIA Roadmap. |
| [3] | Design and Test Chapter, National Technology Road Map, 1997, available on the Web (URL: www.sematech.org). |
| [4] | "Sematech Test Method Evaluation Data Summary Report, " Sematech Project S-121, version 1.4.1, 1/30/96. |
| [5] | S.C. Ma, P. Franco, and E.J. McCluskey, "An Experimental Chip to Evaluate Test Techniques Experiment Results," Proceedings 1995 Int. Test Conference, pp. 663-672, Washington, D.C., Oct. 23-25, 1995. |
| [6] | A. J. van deGoor, Testing Semiconductor Memories, Theory and Practice, John Wiley and Sons, Ltd, England, 1991. |
| [7] | A. Meixner and J. Banik, "Weak Write Test Mode: An SRAM Cell Stability Design for Test Technique," Proc. 1996 Int. Test Conf., pp. 309-318. |
| [8] | A. Carbine and D. Feltham, "PentiumŪ Pro Processor Design for Test and Debug," IEEE International Test Conference, 1997, pp. 294-303. |