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Intel Technology Journal
Copyright  2009 Intel Corporation, All Rights Reserved

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     <title>Intel Technology Journal</title>
	 <link>http://rss.intel.com/click/~rss-158241-c0/www.intel.com/technology/itj/</link>
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	 <description>Featuring Intel's recent research and development</description>
	 <language>en-us</language>
	 <copyright>Copyright  2009 Intel Corporation, All Rights Reserved</copyright>
	 <pubDate>Tue, 14 Jul 2009 02:15:53 PDT</pubDate>
	 <lastBuildDate>Fri, 10 Jul 2009 11:05:22 PDT</lastBuildDate>
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		<title>Intel Technology Journal</title>
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     <item>
		<title>Enhanced Detection of Malware</title>
		<link>http://rss.intel.com/click/~rss-158241-c1-210760/www.intel.com/technology/itj/2009/v13i2/ITJ9.2.1-Malware.htm</link>
		<description>&lt;img alt='' height='1' width='1' src='http://rss.intel.com/click/~rss-158241-i1-210760/0' /&gt;
We present a cloud-computing-based architecture that improves the resiliency of the existing solutions, and we describe our prototype that is based on existing Intel platforms.</description>
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		<pubDate>Tue, 14 Jul 2009 02:15:53 PDT</pubDate>
	 </item>
	 
     <item>
		<title>Protecting Critical Applications on Mobile Platforms</title>
		<link>http://rss.intel.com/click/~rss-158241-c1-210760/www.intel.com/technology/itj/2009/v13i2/ITJ9.2.2-Launch.htm</link>
		<description>&lt;img alt='' height='1' width='1' src='http://rss.intel.com/click/~rss-158241-i1-210760/0' /&gt;
In this article, we describe our research prototype, P-MAPS, a processor-measured service layer that dynamically reduces the trusted computing base and verifiably improves the runtime security of user’s applications, without interrupting the typical operation of the user OS.</description>
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		<pubDate>Tue, 14 Jul 2009 02:15:53 PDT</pubDate>
	 </item> 
	 
     <item>
		<title>Providing a Safe Execution Environment</title>
		<link>http://rss.intel.com/click/~rss-158241-c1-210760/www.intel.com/technology/itj/2009/v13i2/ITJ9.2.3-Safe-Execution-Environment.htm</link>
		<description>&lt;img alt='' height='1' width='1' src='http://rss.intel.com/click/~rss-158241-i1-210760/0' /&gt;
This article describes research on creating a secure execution zone (SEZ) for executing software agents in a secure manner on a computer system.</description>
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		<pubDate>Tue, 14 Jul 2009 02:15:53 PDT</pubDate>
	 </item> 

     <item>
		<title>New Processor Instructions for Accelerating Encryption and Authentication Algorithms</title>
		<link>http://rss.intel.com/click/~rss-158241-c1-210760/www.intel.com/technology/itj/2009/v13i2/ITJ9.2.4-Crypto-Accelerator.htm</link>
		<description>&lt;img alt='' height='1' width='1' src='http://rss.intel.com/click/~rss-158241-i1-210760/0' /&gt;
We present a new set of processor instructions for accelerating Advanced Encryption Standard (AES) encryption and decryption, and for accelerating AES-Galois Counter mode (AES-GCM) authenticated encryption.</description>
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		<pubDate>Tue, 14 Jul 2009 02:15:53 PDT</pubDate>
	 </item> 

     <item>
		<title>https://everywhere! Encrypting the Internet</title>
		<link>http://rss.intel.com/click/~rss-158241-c1-210760/www.intel.com/technology/itj/2009/v13i2/ITJ9.2.5-Encrypting-the-Internet.htm</link>
		<description>&lt;img alt='' height='1' width='1' src='http://rss.intel.com/click/~rss-158241-i1-210760/0' /&gt;
In this article, we present new technologies and results that show the economy of using general-purpose hardware for high-volume HTTPS traffic. We show that these advances provide web services the tools to greatly reduce the cost of implementing HTTPS for all their HTTP traffic.</description>
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		<pubDate>Tue, 14 Jul 2009 02:15:53 PDT</pubDate>
	 </item> 

     <item>
		<title>Recent Contributions to Cryptographic Hash Functions</title>
		<link>http://rss.intel.com/click/~rss-158241-c1-210760/www.intel.com/technology/itj/2009/v13i2/ITJ9.2.6-Hash.htm</link>
		<description>&lt;img alt='' height='1' width='1' src='http://rss.intel.com/click/~rss-158241-i1-210760/0' /&gt;
In this article, we provide the background to understand what a hash function is and what problems it addresses. We then describe and contrast two radically different designs entered in the NIST competition, Skein and Vortex..</description>
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		<pubDate>Tue, 14 Jul 2009 02:15:53 PDT</pubDate>
	 </item>

     <item>
		<title>Enhanced Privacy ID: A Remote Anonymous Attestation Scheme for Hardware Devices</title>
		<link>http://rss.intel.com/click/~rss-158241-c1-210760/www.intel.com/technology/itj/2009/v13i2/ITJ9.2.7-Attestation.htm</link>
		<description>&lt;img alt='' height='1' width='1' src='http://rss.intel.com/click/~rss-158241-i1-210760/0' /&gt;
Enhanced Privacy ID (EPID) is a cryptographic scheme that enables the remote authentication of a hardware device while preserving the privacy of the device owner.  In this article, we discuss hardware authentication and present usage examples.</description>
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		<pubDate>Tue, 14 Jul 2009 02:15:53 PDT</pubDate>
	 </item>

     <item>
		<title>Network Security: Challenges and Solutions</title>
		<link>http://rss.intel.com/click/~rss-158241-c1-210760/www.intel.com/technology/itj/2009/v13i2/ITJ9.2.8-Network-Security.htm</link>
		<description>&lt;img alt='' height='1' width='1' src='http://rss.intel.com/click/~rss-158241-i1-210760/0' /&gt;
In this article we first explore the motivation for protocol security solutions, ones that are capable of protecting data in transit. We describe several solutions, at various layers of the open systems interconnection (OSI) stack, addressing several key network and platform threats.</description>
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		<pubDate>Tue, 14 Jul 2009 02:15:53 PDT</pubDate>
	 </item>
	
     <item>
		<title>The Dark Cloud: Understanding and Defending against Botnets and Stealthy Malware</title>
		<link>http://rss.intel.com/click/~rss-158241-c1-210760/www.intel.com/technology/itj/2009/v13i2/ITJ9.2.9-Cloud.htm</link>
		<description>&lt;img alt='' height='1' width='1' src='http://rss.intel.com/click/~rss-158241-i1-210760/0' /&gt;
In this article, we present an overview of the state of the art of botnets and stealthy malware, then develop and present several promising anti-botnet defense strategies that specifically target current and emerging trends in botnet development.</description>
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		<pubDate>Tue, 14 Jul 2009 02:15:53 PDT</pubDate>
	 </item>

     <item>
		<title>Decentralized Trust Management for Securing Community Networks</title>
		<link>http://rss.intel.com/click/~rss-158241-c1-210760/www.intel.com/technology/itj/2009/v13i2/ITJ9.2.10-Community.htm</link>
		<description>&lt;img alt='' height='1' width='1' src='http://rss.intel.com/click/~rss-158241-i1-210760/0' /&gt;
In this article, we discuss the fundamental difficulties and system requirements for decentralized trust management, and we propose new technologies that enable the bootstrapping of trust, and, subsequently, the calculation of trust metrics that are better suited to these domains.</description>
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		<pubDate>Tue, 14 Jul 2009 02:15:53 PDT</pubDate>
	 </item>
	 	  	 	 
     <item>
		<title>Performance Analysis of the Intel System Controller Hub (Intel SCH) US15W</title>
		<link>http://rss.intel.com/click/~rss-158241-c1-210760/www.intel.com/technology/itj/2009/v13i1/01performance-analysis-SCH.htm</link>
		<description>&lt;img alt='' height='1' width='1' src='http://rss.intel.com/click/~rss-158241-i1-210760/0' /&gt;
This article takes a systematic look at the architecture of the Intel SCH US15W. It investigates the performance of the Intel SCH backbone and the effects that that backbone has on PCI Express* (PCIe*) bandwidth in particular.</description>
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		<pubDate>Sat, 07 Mar 2009 02:15:53 -0400</pubDate>
	 </item>

     <item>
		<title>Configuring and Tuning for Performance on Intel 5100 Memory Controller Hub Chipset Based Platforms</title>
		<link>http://rss.intel.com/click/~rss-158241-c1-210760/www.intel.com/technology/itj/2009/v13i1/02tuning-Intel-5100.htm</link>
		<description>&lt;img alt='' height='1' width='1' src='http://rss.intel.com/click/~rss-158241-i1-210760/0' /&gt;
This article presents performance-related architecture topics for the Intel 5100 MCH chipset to assist system architects in designing a high performance solution. It will help engineers and architects make decisions with an awareness of performance implications, such as CPU population, memory configuration, and I/O device placement.</description>
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		<pubDate>Sat, 07 Mar 2009 02:15:53 -0400</pubDate>
	</item>

     <item>
		<title>Solid State Drive Applications in Storage and Embedded Systems</title>
		<link>http://rss.intel.com/click/~rss-158241-c1-210760/www.intel.com/technology/itj/2009/v13i1/03SSDs-for-Embedded.htm</link>
		<description>&lt;img alt='' height='1' width='1' src='http://rss.intel.com/click/~rss-158241-i1-210760/0' /&gt;
Solid State Drives (SSDs) have found a place to assist in capacity density, which is the total gigabytes/terabytes per RU, per watt, and per thermal unit waste heat.</description>
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		<pubDate>Sat, 07 Mar 2009 02:15:53 -0400</pubDate>
	</item>
	
     <item>
		<title>Fanless Design for Embedded Applications</title>
		<link>http://rss.intel.com/click/~rss-158241-c1-210760/www.intel.com/technology/itj/2009/v13i1/04Fanless-Cooling.htm</link>
		<description>&lt;img alt='' height='1' width='1' src='http://rss.intel.com/click/~rss-158241-i1-210760/0' /&gt;
This article emphasizes analytical hand calculation for first-order approximations and provides computational fluid dynamics (CFD)
simulation techniques to determine Intel architecture feasibility in fanless systems.</description>
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		<pubDate>Sat, 07 Mar 2009 02:15:53 -0400</pubDate>
	</item>

     <item>
		<title>Security Acceleration, Driver Architecture and
Performance Measurements for Intel EP80579 Integrated
Processor with Intel QuickAssist Technology</title>
		<link>http://rss.intel.com/click/~rss-158241-c1-210760/www.intel.com/technology/itj/2009/v13i1/05Crytographic-Security.htm</link>
	<description>&lt;img alt='' height='1' width='1' src='http://rss.intel.com/click/~rss-158241-i1-210760/0' /&gt;
This article describes how the Intel QuickAssist Technology components in the Intel(R) EP80579 Integrated Processor offload the compute-intensive cryptographic operations from the Intel(R) architecture core to a low-power cryptographic accelerator,</description>
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		<pubDate>Sat, 07 Mar 2009 02:15:53 -0400</pubDate>
	</item>

     <item>
		<title>Methods and Applications of System Virtualization using
Intel Virtuali zation Technology (Intel VT)</title>
		<link>http://rss.intel.com/click/~rss-158241-c1-210760/www.intel.com/technology/itj/2009/v13i1/06Virtualization.htm</link>
		<description>&lt;img alt='' height='1' width='1' src='http://rss.intel.com/click/~rss-158241-i1-210760/0' /&gt;
This article provides an overview of the evolution of hypervisor architectures, including both software and hardware trends, and how they affect the security and practicality of system virtualization. We shall also discuss a range of compelling applications for secure virtualization across a variety of communities of interest.</description>
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		<pubDate>Sat, 07 Mar 2009 02:15:53 -0400</pubDate>
	</item>

     <item>
		<title>Building and Deploying Better Embedded Systems with Intel
Active Management Technology (Intel AMT)</title>
		<link>http://rss.intel.com/click/~rss-158241-c1-210760/www.intel.com/technology/itj/2009/v13i1/07AMT-in-Embedded.htm</link>
		<description>&lt;img alt='' height='1' width='1' src='http://rss.intel.com/click/~rss-158241-i1-210760/0' /&gt;
This article provides a high level description of Intel Active Management Technology, explains some key benefits of the technology and presents a case study of how Intel AMT can be successfully applied to point-of-sale workstations to offer enhanced energy efficiency and advanced remote management capabilities to retail IT enterprises.</description>
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		<pubDate>Sat, 07 Mar 2009 02:15:53 -0400</pubDate>
	</item>

     <item>
		<title>Implementing Firmware for Embedded Intel Architecture
Systems: OS-Directed Power Management (OSPM) through the
Advanced Configuration and Power Interface (ACPI)</title>
		<link>http://rss.intel.com/click/~rss-158241-c1-210760/www.intel.com/technology/itj/2009/v13i1/08Embedded-firmware.htm</link>
		<description>&lt;img alt='' height='1' width='1' src='http://rss.intel.com/click/~rss-158241-i1-210760/0' /&gt;
This article explores how ACPI has provided efficiencies over APM and BIOS-directed power management and provides a condensed overview of APCI technology.</description>
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		<pubDate>Sat, 07 Mar 2009 02:15:53 -0400</pubDate>
	</item>

     <item>
		<title>A Real-Time HPC Approach for Optimizing Intel Multi -Core
Architectures</title>
		<link>http://rss.intel.com/click/~rss-158241-c1-210760/www.intel.com/technology/itj/2009/v13i1/09Real-Time-Math.htm</link>
		<description>&lt;img alt='' height='1' width='1' src='http://rss.intel.com/click/~rss-158241-i1-210760/0' /&gt;
This article presents findings that demonstrate how a novel approach with Intel hardware and software technology is allowing for real-time high-performance computing (HPC) in order to solve engineering problems with multi-core processors that were not possible only five years
ago.</description>
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		<pubDate>Sat, 07 Mar 2009 02:15:53 -0400</pubDate>
	</item>

     <item>
		<title>Digital Signal Processing on Intel Architecture</title>
		<link>http://rss.intel.com/click/~rss-158241-c1-210760/www.intel.com/technology/itj/2009/v13i1/10Embedded-DSP.htm</link>
		<description>&lt;img alt='' height='1' width='1' src='http://rss.intel.com/click/~rss-158241-i1-210760/0' /&gt;
This article explores the main differences between traditional digital signal processors and modern Intel general purpose processor  architectures and gives some orientation on how DSP engineers can most effectively take advantage of the resources available in Intel processors.</description>
		<guid isPermaLink="true">http://rss.intel.com/click/~rss-158241-c1-210760/www.intel.com/technology/itj/2009/v13i1/10Embedded-DSP.htm</guid><pubDate>Sat, 07 Mar 2009 02:15:53 -0400</pubDate>
	</item>

     <item>
		<title>IA-32 Features and Flexibility for Next-Generation Industrial
Control</title>
		<link>http://rss.intel.com/click/~rss-158241-c1-210760/www.intel.com/technology/itj/2009/v13i1/11Industrial-Automation.htm</link>
		<description>&lt;img alt='' height='1' width='1' src='http://rss.intel.com/click/~rss-158241-i1-210760/0' /&gt;
This article describes a suggested design approach for an open control platform using the IntelR Atom processor. It illustrates how these new processors provide the benefits of IA-32 open architectures while at the same time meeting the power and cost envelope associated with designs at the control level in industrial factory automation.</description>
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		<pubDate>Sat, 07 Mar 2009 02:15:53 -0400</pubDate>
	</item>

     <item>
		<title>Low Power Intel Architecture Platform for In-Vehicle</title>
		<link>http://rss.intel.com/click/~rss-158241-c1-210760/www.intel.com/technology/itj/2009/v13i1/12IVI-Open-Platform-D1.htm</link>
		<description>&lt;img alt='' height='1' width='1' src='http://rss.intel.com/click/~rss-158241-i1-210760/0' /&gt;
This article presents the architecture of this platform for the IVI market segment powered by the IntelR Atom processor family of low power embedded processors and standards-based platform hardware and software ecosystem.</description>
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		<pubDate>Sat, 07 Mar 2009 02:15:53 -0400</pubDate>
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