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Volume 12, Issue 03

Original 45nm Intel® Core™ Microarchitecture


Intel Technology Journal - Featuring Intel's recent research and development

ISSN 1535-864X DOI 10.1535/itj.1203.03

  • Volume 12
  • Issue 03
  • Published November 7, 2008

Original 45nm Intel® Core™ Microarchitecture

  Section 14 of 15  

Improvements in the Intel® Core™2 Processor Family Architecture and Microarchitecture

REFERENCES

[1] Nisar, A., Ekpanyapong, M., Valles, A., and Sivakumar, K. Original 45nm Intel® Core™2 Processor Performance, Intel Technology Journal, 2008 Vol. 12, No. 3, 2008.

[2] Jha A., Yee D. Increasing Memory Throughput With Intel® Streaming SIMD Extensions 4 (Intel(4) SSE4) Streaming Load http://softwarecommunity.intel.com/articles/eng/1248.htm.

[3] Intel® 64 and IA-32 Architectures Optimization Reference Manual At http://www.intel.com/products/processor/manuals/.

[4] Intel® 64 and IA-32 Architectures Software Developer's Manual At http://www.intel.com/products/processor/manuals/.

[5] Atkins D.E. Higher radix division using estimates of the divisor and partial remainders. IEEE Transactions on Computers 1968; C-17: 925–934.

[6] Parhami B. Tight upper bounds on the minimum precision required of the divisor and the partial remainder in high-radix division. IEEE Transactions on Computers, Vol. 52, No.: 11, November 2003, pp. 1509–1514.

[7] Wey C.-L., Wang C.-P. Design of a fast radix-4 SRT divider and its VLSI implementation. Computers and Digital Techniques, IEE Proceedings, Vol. 146, No. 4, July 1999, pp. 205–210.

[8] “ Design issues in radix-4 SRT square root & divide unit” Burgess, N.; Hinds, C.; “Signals, Systems and Computers.” Conference Record of the Thirty-Fifth Asilomar Conference, Vol. 2, November 4–7, 2001, pp. 1646–1650.

  Section 14 of 15  

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