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Intel's 45nm CMOS Technology
PREFACE Q2'08
By Lin Chao
Publisher and Editor, Intel Technology Journal
Hello. This Q2'08 Intel Technology Journal (Vol. 12, Issue 2) covers Intel's 45nm CMOS technology which proved pivotal to the advancement in silicon processes technology by extending Moore's Law.
On a personal note, it has been a privilege for the past 12 years to serve as your publisher and editor for this Intel Technology Journal (ITJ). This is my last issue as publisher and editor. My thanks to the many of you who have read ITJ since it went online in 1997. ITJ was a pioneer and was among the first technical journals to publish on the Web, and use the Web as its sole publishing means. I remember in 1996 making the decision to publish the ITJ solely online and at the time thinking the Web is risky, but worth trying. Time has shown that the Web was the right decision!
In future, this Journal will be integrated into Intel Press publications.
ITJ has been a repository of Intel technical advancements. ITJ started in 1979 and we are making preparations to make some of the earliest papers available for sharing. I wish to thank the authors who shared with a world-wide community their knowledge and insights about how the technology came into being; after all, who knows better than the actual people who worked on it? Indeed, the authors are also the people who worked directly on the technology. To the authors, I am proud and grateful to have gotten to know you and shared your passions and the heights and lows of advancing the forefront of technology. Thank you to this journal's dedicated team, to Intel's management for your support, and the world-wide community of readers and authors; I am very proud of what we created together. Thank you.
This Intel Technology Journal (Vol. 12, Issue 2) focuses on Intel® 45nm high-k metal gate silicon technology. To quote Gordon Moore, co-founder of Intel Corporation, "this is the biggest change in transistor technology in 40 years." In this journal there are seven papers that give in-depth coverage to three key aspects of the technology's transistors and interconnects, variation and design for manufacturability, and packaging and reliability. The new process also produces Intel's first completely lead-free microprocessor products.
Two papers look at transistors and interconnects. The first paper reviews, for 45nm technology, the details of the high-k+metal gate transistors that have been introduced for the first time into high-volume manufacturing. The second paper introduces the issues associated with on-die interconnects and describes how they are addressed on Intel's 45nm high-performance logic process technology. The on-die interconnect stack for Intel's 45nm process generation delivers a 2X higher area density, a 10% lower average capacitance, and improved power distribution.
The next three papers look at manufacturing issues related to variations and designs. The third paper states that process variation is not an insurmountable barrier to Moore's Law, but is simply another challenge to be overcome. This is illustrated with data from the 45nm process generation where process variation is shown to be at least equivalent to (and in many cases better than) process variation in the 65nm- and 90nm-process generations.
The fourth paper looks at 45nm SRAM as a lead test vehicle. Every new generation of process technology at Intel is developed and certified using an SRAM-based "X-chip." X6 is the technology lead vehicle used for the 45nm technology serving as a platform for the co-optimization of circuit design and process technology for SRAMs as well as critical design evidence for products. The fifth paper reviews the complex dependencies of design and process to be able to manufacture into microprocessor products. Co-optimization between design and process is required for a highly manufacturable process technology. This paper discusses how cooperation between design and process meets the challenges for maintaining Moore's Law while delivering fast ramp-up and high yields. The variation, density, and yields on the 45nm process show the success of this Design for Manufacturing (DFM) methodology.
The final two papers look at packaging and reliability. The sixth paper reviews in depth the reliability of Intel's 45nm HK+MG transistors demonstrating that these devices deliver reliability comparable to conventional SiO2 devices at ~30% higher operating fields with negligible stress-induced leakage current (SILC) degradation.
In the seventh and final paper, we shared some of the key challenges associated with the development of a high-volume manufacturing compatible assembly process for packaging Intel's 45nm, completely lead-free devices. Key technical challenges were addressed through development of novel FLI solders, fluxing material, and process solutions. Small form-factor packaging challenges were overcome by a series of innovative materials and process changes to achieve a reduction in form factor while meeting the technology reliability goals. This enables Intel's continuing leadership in thin and light notebooks and smart phone devices.
We are very proud to have eliminated the use of lead in this technology which also makes Intel a leader in achieving environmentally green products.