Intel's 45nm CMOS Technology

  Section 9 of 10  

Flip-Chip Packaging Technology for Enabling 45nm Products

REFERENCES

[1] "Introducing the 45nm next generation Intel core microarchitecture." Appeared in print on www.intel.com/technology/architecture-silicon/intel64

[2] Intel Press Release www.intel.com/consumer/learn/mids/centrino-atom-detail.htm

[3] Mark Bohr "Intel's 65nm logic technology." 65nm Press Release August 2004.

[4] B. Chandran, R. Mahajan, M. Bohr, and Q. Vu, "The Mechanical Side of Ultra-low k: Can it Take the Strain?" FUTURE FAB International, 2004, pp. 121–124.

[5] K. Mistry et al., "A 45nm logic technology with high K+Metal gate transistors, Strained Silicon, 9 Cu Interconnect layers, 193nm dry patterning and 100% Pb-free packaging." IEDM Technical Digest, 2007, pp. 247–250.

[6] M.K. Schweibert and W. L.K. Leong, "Underfill flow as viscous flow between parallel plates driven by capillary action." IEEE transactions on CPMT - Part C. Volume 19, No. 2, 1996.

  Section 9 of 10  

Back to Top