Intel's 45nm CMOS Technology

Flip-Chip Packaging Technology for Enabling 45nm Products

Z-HEIGHT REDUCTION

Industry benchmark trends indicate that overall package height in high-end smart phones are typically less than 1mm. While most of these packages to date are wirebonded and overmolded, there is an increased need to develop high I/O flip-chip packages that have z-heights of less than 1mm. In order to achieve significant package height reduction we discuss die thinning and the use of thinner/coreless substrates.

Results and Discussion

The typical thickness of a 12 inch wafer is ~750-800um. Since the active silicon needed for functioning of the device is less than 20-30um, a significant reduction in z height can be achieved by die thinning. Wafer backgrinding is common for devices used in stacked die, wirebond packaging technology, where die thinning down to 50-75um is routinely employed in high-volume manufacturing. However, die thinning of a high-density bumped flip-chip die is a significant challenge. Figure 17 shows the SEM image of a bumped wafer with Cu-bumps with the bump height nominally ~50 um.

Figure 17: SEM image of a Cu bumped wafer
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In order for the backgrinding process to work effectively, it is critical for the backgrinding tape to completely encapsulate the bumped wafer without any voids. This is essential since the presence of voids or the inability of the tape to completely encapsulate the bumps can lead to cracking of the wafer or non-uniform backgrinding. In addition to the encapsulation, it is also critical that the tape be removed without leaving any residue or damaging the Cu-bump/BLM during the tape peel step. In order to achieve this critical balance of lamination, uniform backgrinding and clean removal post backgrinding, a multi-layer adhesive, UV, curable tape with a soft backing layer was developed. The backgrind tape is laminated to the wafer, and the hardness of the multilayer adhesive layer contacting the wafer surface is well controlled to allow complete encapsulation of the bumps. After the backgrinding process, the tape is exposed to UV cure, leading to cross-linking and hardening of the multi-layer adhesive. This allows for easy detaping of the tape from the backgrinded wafer, since the harder x-linked adhesive can easily delaminate from the wafer/bump surface. Using this technology, Intel has been able to develop a high-volume manufacturing process for wafer thinning 12-inch, high-density bumped wafers down to 75um.

In addition to wafer thinning, the other element that can enable further z height reduction is minimizing the substrate thickness. In the case of the organic substrate, a standard build-up core of ~800um is used for typical packages. This core thickness in the substrate is typically selected in order to balance the electrical requirements of the package and its ability to go through the assembly line and SMT processing. In order to decrease the overall thickness of the package, one of the approaches is to reduce the thickness of the core layer in the package. Depending on the need for the overall package thickness, either die thinning or substrate thinning, or both, can be employed to produce the overall desirable thickness. With the combination of die thinning and substrate thinning, Intel now has the capability to produce flip-chip packages with package heights that are 33% less than standard packages (Figure 18).

Figure 18: Comparison of a standard package z-height with a thin core-thin die package
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Board Level Interconnect

Intel's 45nm technology is useful for a wide variety of products from servers to mobile devices. In order to meet the size requirements of ultra mobile personal computers and mobile Internet devices, the 45nm packaging technology had to scale the physical size of the packages to meet the demands of the ultra mobile products.

Scaling down the size of these packages while maintaining the product functionality of Intel Architecture requires the board-level interconnect to scale as well. In the case of the Intel® Atom™ processor, the ball pitch scaled down to 0.6mm from a 0.8 to 1.27mm pitch for PCs. This scaling creates two key challenges: routing the signals on the board and ensuring a robust solder joint.

Figure 19: Cross section of a Type 3 motherboard
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Traditional PCs utilize a Type 3 motherboard that is characterized by mechanically drilled vias as shown in Figure 19. In mobile stripline routing, the signals that come out of the package have to travel through these vias on their way out of the package. Unfortunately, these mechanically drilled vias do not scale well and limit the package ball pitch to approximately 0.8mm. The routing issue is solved by using High Density Interconnect (HDI) motherboards shown in Figure 20. HDI boards contain one or more layers that are connected to other layers through microvias. As the name implies, the laser drilled microvias are significantly smaller than the mechanically drilled vias and allow the signals to break out from the package.

Figure 20: Cross section of an HDI motherboard
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Solder joint reliability is the other board-level challenge with SFF packages. By the very nature of their use, mobile products are subject to drops. The smaller solder joints of SFF packages have less mass to handle these mechanical stresses. Gluing the corners of the packages provides the additional strength and mechanical margin for the mobile drop condition as shown in Figure 21.

Figure 21: Corner glue provides mechanical margin for mobile drop condition
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