Intel's 45nm CMOS Technology

Flip-Chip Packaging Technology for Enabling 45nm Products

PACKAGE SIZE REDUCTION IN XY

The top surface of a flip-chip package contains the silicon die attached to the organic substrate and is underfilled with an epoxy material. The underfill material's primary function is to protect the flip-chip solder joints from failing due to stresses induced by the CTE mismatch between the die and the package during processing and use. The underfill material can occupy a significant area on the package as shown in Figure 13.

Figure 13: Example of underfill spread on a flip-chip CPU package
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One of the key factors that controls the underfill spread on the package are the flow characteristics of the underfill material. Underfill flow under the die is driven by capillary flow. A line of underfill material is dispensed next to the die at high temperature, and capillary pressure in the material pulls the material under the die. In order to minimize the underfill spread away from the die, it is critical to increase the flow speed of the underfill material under the die, as schematically illustrated in Figure 14.

Figure 14: Competing forces for underfill spread under the die vs. away from die
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In an idealized case, underfill flow can be modeled as flow between parallel plates [6], where the time to fill for an underfill between parallel plates can be calculated using this equation:

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where y is the surface tension of the underfill material, μ is the viscosity of the material, h is the gap between the plates, θ is the angle of wetting between the underfill and two surfaces, and L is the flow distance. Based on this elementary flow model, minimizing the μ/y ratio can improve the flow speed of the underfill material.

Results and Discussion

A series of formulations with surface tension of the underfill material varying from ~20 dynes/cm² to 40 dynes/cm² at 110°C, and viscosities varying from 0.5 poise to 1.6 poise, were tested in a simple parallel plate flow experiment. Figure 15 shows the time to flow versus distance results for the formulations tested.

Based on the data from this simple flow test, it was observed that over a distance of ~15mm, significant reduction in flow time could be observed. These formulations were then tested on a package, leading to significant improvement on the flow speed of the material and therefore a reduction in the underfill spread on the package as shown in Figure 16.

Figure 15: Flow time vs. distance for various underfill materials
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Figure 16: Underfill epoxy spread on the die with normal UF and optimized UF
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The underfill material is a highly engineered epoxy-silica composite material with optimum thermo-mechanical properties (Tg, CTE, Modulus, etc.) to minimize stress transfer to die, and to prevent bump fatigue and die-cracking. In addition, the underfill material is also designed for toughness and adhesion to various interfaces (solder resist on substrate, passivation on die, Cu-bump, FLI solder, and silicon) under Pb-free, reflow conditions. These requirements lead to a very specific choice of epoxy resin chemistries that can be used in underfill material development. Adding the challenge of improved flow with higher μ/Y ratio required careful study of the surface tension/viscosity of each of the resin components in the material and to the selection of the right combination of components in order to provide good flow, and yet not compromise the reliability of the underfill. As shown in Figure 16, optimization of the μ/Y ratio of the underfill is very influential in minimizing the underfill spread on the package. However, it is also critical to note that there is a limit to how much the underfill viscosity can be reduced and to how much the surface tension of the underfill can be increased beyond which other effects take over. These can lead to increased spread of the underfill on the sides (due to very low viscosity of the material) and de-wetting of the underfill from the substrate, due to too high a surface tension of the material. Using this approach, new underfill formulations have been developed and deployed in high volume for enabling small form-factor, flip-chip packages. Utilization of this technology in combination with other novel process and design optimization approaches have led to significant reduction (up to 60%) in the package size for small, form-factor packages.

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