Intel's 45nm CMOS Technology

  Section 4 of 10  

Flip-Chip Packaging Technology for Enabling 45nm Products

FORM FACTOR MANAGEMENT

Development of small form factor packaging technologies required significant engineering effort in addition to the challenges involved with the integration of Pb-free, 45nm silicon technology. Key technical challenges include package size reduction in XY dimension and a reduction in the thickness of the package itself, by reducing die thickness and substrate thickness. Thin die challenges include the thinning process, stress-induced electrical property changes, and package warpage concerns. In addition, wafer thinning would require ensuring relief of residual stresses caused by the thinning process and protecting the die from chipping and cracking during wafer thinning and die singulation. Handling of the significantly warped thin wafer and die is another key challenge. A thin package with thin die is prone to warpage due to its low stiffness. Decreases in die thickness can make this problem worse, impacting the board assembly yield. Making the problem even more challenging is the need for a more coplanar BGA ball field to enable board assembly with finer BGA pitch. Solutions for these challenges required significant innovation and re-engineering in packaging material and process technologies. The approach, along with a few of the examples, is discussed below.

  Section 4 of 10  

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