Intel's 45nm CMOS Technology

Flip-Chip Packaging Technology for Enabling 45nm Products

FIRST-LEVEL LEAD-FREE INTERCONNECT

The 45nm process incorporates high-K+metal gate (HiK+MG) transistors for the first time along with third-generation strained silicon, nine copper interconnect layers, 193nm dry patterning, and 100% Pb-free packaging. A complete overview of the 45nm silicon process technology is given in [5]. The die far back-end architecture makes use of a very thick metal 9 (TM9) layer and a polymer dielectric, as shown in Figure 2. The integration of Pb-free solder with the novel TM9 architecture that employed a new dielectric/passivation material posed new challenges for material compatibility and M9 stack reliability, in addition to low-k dielectric material cracking/delamination. These issues were fully resolved through an iterative optimization of the metal interconnect, package design, materials, and processes within the fab and assembly.

Figure 2: SEM depicting the M9 and V9 layers: M9/V9 is significantly thicker than all the other die metal layers
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Challenges of First-level, Lead-free Interconnect

Compared to their leaded counterparts, tin-rich, Pb-free solder materials possess physical, metallurgical, and mechanical properties that pose significant challenges to flip-chip assembly and reliability. Their higher melting point (~30°C higher than SnPb) leads to an increase in the thermal expansion mismatch between silicon die and organic packaging and induces higher stress in the FLI solder joint compared to previous generations. The intrinsically higher mechanical stiffness of Pb-free solder and dramatically reduced mechanical strength of low-k dielectric materials of the silicon backend structures led to significant assembly challenges such as die Interlayer Dielectrics (ILD) cracking and occasional solder joint interfacial delamination (Figure 3). The inferior wettabililty of the Pb-free solder results in a reduced solder wicking with die copper column during chip attachment (Figure 4), and it considerably increases sensitivity to assembly-interaction-related failures, such as solder joint interconnect opens and non-wets, which require more stringent solder bump dimensional control. To achieve a healthy assembly yield for our Pb-free SAC process, tolerances, and sensitivities several new manufacturing process parameters had to be thoroughly studied, e.g., bump height variation and bump-level defects. Solder joint voiding is also of concern, as the outgassing of soldering flux residues becomes retarded due to higher surface tension and is accelerated by the ease of the tin oxide formation of the liquid solder.

Figure 3: Solder joint delamination along solder/surface finish interface
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Figure 4: Reduced wettability of SnAgCu with die Cu-bump leads to a reduced solder joint collapse
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The use of existing chip-attach fluxes developed for leaded solder alloys can cause significant defects, such as solder voids and interfacial nonwets, in the Pb-free FLI joints, due to the higher thermodynamic stability of the oxides in Pb-free solders. Furthermore, the need for higher peak temperature and Time Above Liquidus (TAL) for Pb-free solder can cause significantly higher flux residue to remain on the packages. Both these factors necessitated the development of a new flux that needed to be highly active in order to remove the thermodynamically stable tin oxides and improve wettability of solder to Cu. These new fluxes also had to have significantly reduced outgassing at reflow peak temperature and the TAL in order to reduce FLI voiding and in order to leave a residue that was easily cleanable by the hot water during the deflux process. In addition, the new flux formulations had to be compatible with the substrate solder resist material and the new die passivation material, have sufficient tackiness to prevent die misalignment and substrate solder bridging, and be capable of being printed or sprayed on the substrate.

The chip-attach process for flip-chip packaging follows these main steps: flux application, chip placement, reflow of chip joints, and cleaning of flux residue. Intel has been printing the flux in CPU packaging for many years. This process involves printing flux through an aperture opening in a stencil on the substrate bump area. This flux application process has worked very well for high-volume applications up to this point, but it has reached its limit for larger die sizes and multiple dies on a package. Using a flux printing process for larger and multiple dies can lead to scraping of substrate bumps that could potentially cause reliability problems such as non-wets, limited performance because of decreased maximum current-carrying capacity (referred to as IMAX), and reduced yield.

An out-of-the-box approach was pursued to enable a spray flux application process (SPRINT) by using a print flux material that was designed to be highly viscous at room temperature so it does not flow.

Figure 5: Conceptual description of "SPRINT" process—spraying a Print flux material using a dispenser
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The print flux material is a non-Newtonian fluid with shear thinning properties. Several equipment and process changes had to be made to get the required dispense characteristics (Figure 5). An optimum fluid path heater design equipped with sufficient flux hold-up volume and heated to the target temperature prior to dispensing (Figure 6) was needed to enable a stable and capable dispensing process. Significant process characterization work had to be carried out to optimize different dispense parameters such as fluid and atomizing coaxial air-pressure, dispense temperature, dispense height and width, and line speed. The goal was to get just the right amount of flux on the substrate bumps: too little flux led to poor quality joints between substrate and die bumps, and too much flux caused die misalignment during the reflow process. All the process characterization work led to the fundamental understanding of the impact of flux dispense parameters on die misalignment yield and FLI joint quality.

Figure 6: Schematic of "SPRINT" (spraying the print flux) process
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Results and Discussions

To overcome the challenges of integrating Pb-free, flip-chip packaging with 45nm silicon, significant work was carried out from design, materials, processing, and metrology perspectives. Based on over five years of research experience on Pb-free materials, Intel selected Sn-Ag-Cu solder metallurgy as the flip-chip die attachment material. This material has showed significant improvement in solder-joint quality compared to the other more commonly used Pb-free alloys in our case.

Enabling the SPRINT process to high-volume manufacturing involved solving several manufacturability issues specific to ease and repeatability of tool maintenance.

The SPRINT process has met yield and reliability goals both during the development of Pb-free packages and during high-volume manufacturing ramp in Intel factories. At the end of the development cycle, the SPRINT process is at 99.5+% in three different Intel sites, and the samples used during the development phase show no die misalignment.

Figures 7, 8, and 9 show the comparison of FLI joint interfacial defects, solder voiding, and electromigration performance between the new flux and previous-generation fluxes. The new flux provides significantly better performance in all three attributes. Figure 10 shows the comparison between leaded (65nm process technology) and Pb-free electromigration performance with optimized materials/process.

Figure 7: Comparison of interfacial defects between old and new fluxes: new flux is significantly better
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Figure 8: Comparison of FLI solder voids between new (left) and old (right) fluxes: new flux is significantly better
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Figure 9: Comparison of electromigration performance between old flux, new flux (print formulation) and new flux (spray formulation): new flux is significantly better
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Figure 10: Comparison of bump electromigration performance of Cu-Sn/Pb and 100% Pb-free FLI
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Figure 11 shows C-mode scanning acoustic microscope (CSAM) images of product units (complete stack-up). Cracking or interface delamination in the ILD or TM9 stack will show up as white or black spots apart form the contrast variation of the underlying pattern. The image on the left was taken after packaging: no contrast areas are observed, showing that the unit is free of cracking and/or interface delamination. These results have been reproduced in high volume, at process extremes, and have been proven to have significant margin through execution of well-designed hammer tests that impart significantly higher stress on the die than typically observed in manufacturing. The image on the right shows that the parts are clean of any issues even after reliability stresses.

Figure 11: C-SAM units of production units: image on the left represents a unit post packaging and the image on the right is a unit post 25 hrs of HAST
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These results indicate that the 45nm technology FLI architecture meets the stringent quality and reliability criteria despite the higher stress induced by Pb-free solders. Intel's FLI architecture with Cu-bumps is very unique and provides significantly better electromigration performance and power distribution performance than typical 100% solder-based FLI interconnects, as shown in Figure 12.

Figure 12: Comparison of bump electromigration performance of high Pb-bumps and Pb-free FLI
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Sn-Ag-Cu solders have better wettability to metal pads, leading to reduced solder voiding, bumping, and assembly solder joint open yield loss. They also possess increased solder joint strength due to the suppression of under-bump nickel barrier layer diffusion and intermetallic growth. SAC solders also possess enhanced electromigration resistance arising from the synergistic reactions of reduced metal diffusion and interfacial defects.

As discussed earlier, the loss of solder joint collapse margins with the advent of Pb-free materials requires more stringent solder bump dimensional control. To achieve this control, solder bumping, flux material, and the reflow process were improved. The substrate C4 solder bump metrology was also modified significantly to screen out bump-level defects at high through-put speeds. Additionally, substrate packaging materials and design were also optimized to accommodate the higher reflow temperature of Pb-free solder to mitigate the associated reliability issues.

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