Intel's 45nm CMOS Technology

Flip-Chip Packaging Technology for Enabling 45nm Products

INTRODUCTION

Intel's 45nm technology portfolio includes the Penryn family of processors, which build on the success of the revolutionary core microarchitecture as well as the family of devices, based on Intel® Centrino® Atom™ processor technology, targeted for mobile Internet device applications. The Penryn family of processors features new dual-core desktop processors, quad-core desktop processors, quad-core server processors, and dual-core mobile processors. These new 45nm processors include features to improve performance at any given frequency: they have up to 50% larger L2 caches and expanded power-management capabilities for new levels of energy efficiency [1]. The Intel® Atom™ processors have been developed from the ground up with the aim of minimizing the power consumption and yet enabling a high-performance fully functional chip for the mobile Internet device segment [2].

The introduction of 45nm products also marks the move to 100% Pb-free packages to meet Intel's environmental performance goals. Lead has been used generously in the past as the primary component of the metal alloy (a mixture of tin and lead) used to electrically connect the silicon processor to the motherboard via an organic package. The interconnect hierarchy is shown in Figure 1.

Figure 1: Schematic of a flip-chip ball grid array (FCBGA) pack
click image for larger view
 

Due to the harmful impact of lead on the environment, however, Intel's engineers engineered a solution to get every last milligram of lead out of the package. The entire First-Level Interconnect (FLI) architecture was reengineered to be 100% Pb-free in a phased approach. In the first phase, Cu bumps were incorporated as part of the 65nm process technology CPUs [3] in place of the more compliant high Pb-bumps on the silicon die. This was followed by tin-silver-copper (SAC) solder in place of eutectic Pb-Sn, as part of the 45nm technology. The new architecture not only meets the stringent quality and reliability requirements of Intel products but also significantly improves bump cracking, bump electromigration, and solder fatigue performance, all of which are crucial to enabling reliable, high-performance microprocessors. Both Cu-bumps and SAC solder on the substrate are much stiffer than their leaded counterparts and impart significantly higher thermomechanical stress on the mechanically-weak, low-dielectric constant materials on the silicon die [4]. The use of a higher number of low-k-based metal layers in the 45nm products for improved interconnect performance further exacerbates the stress-management challenge. These challenges were resolved with an optimization of far back-end architecture, design, materials, and processes in both fab and assembly.

The move towards producing thin and light laptops and the need for improving the processing power in smart phones and mobile Internet devices has led to increased focus on the development of small form-factor, flip-chip package technologies that can accommodate full function, high I/O CPUs. In these market segments, the focus is on reducing the overall form factor of the package. This reduction in space is essential to enable system-level reduction in the motherboard size used in hand-held, mobile Internet device applications [2]. The drive towards smaller form factors places tremendous pressure on minimizing the area occupied by the flip-chip package and requires significant re-engineering of the flip-chip packaging technology.

In this paper we focus on the novel materials and processes that were developed in order to overcome these challenges to achieve 100% Pb-free interconnect as well as a significant reduction in the form factor for flip-chip packages.

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