Intel's 45nm CMOS Technology

Flip-Chip Packaging Technology for Enabling 45nm Products

AUTHORS’ BIOGRAPHIES

Neha Patel
Neha Patel is a Senior Materials Engineer in the Assembly Test Technology Development (ATTD) Group. She has been with Intel for three years and has worked extensively in the area of first-level interconnect polymer materials and thermal interface materials. She obtained her B.A. degree in Physics from St. Xaviers College, Bombay and M.S. and Ph.D. degrees in Physics from Case Western Reserve University, Cleveland, OH. Her e-mail is neha.m.patel at intel.com.

Vijay Wakharkar
Vijay Wakharkar is a Principal Engineer in the ATTD Group and has worked at Intel for 17 years. Vijay received his B.A. degree from the College of Engineering, Poona in 1982 and his Ph.D. degree in Materials Science and Engineering in 1988. Prior to joining Intel, he spent two years as a Post Doctoral Fellow at IBM Almaden Research Center in the Polymer Materials Division. Currently, Vijay is in ATTD's Path-finding Group working on the 1272 Package path-finding programs. Prior to joining the ATTD Path-finding Group in March this year, Vijay was responsible for managing the development and pathfinding of Materials Technologies that end up in ATTD's packaging platforms. He is one of the founding editors of the Intel Assembly Technology and Test Journal (IATTJ) and also serves on Intel's Thermo-mechanical Patent Committee. His e-mail is vijay.s.wakharkar at intel.com.

Sairam Agrahram
Sairam Agrahram is a Group Leader of the Technology Integration Group in ATTD. He has been with Intel for seven years has worked extensively on identifying, understanding, and resolving die package interactions and assembly integration issues. He obtained his bachelors degree in Chemical Engineering from Osmania University, India and a Ph.D. degree in Chemical Engineering from Georgia Institute of Technology, Atlanta, USA.

Nitin Deshpande
Nitin Deshpande is a Senior Process Engineer in the ATTD Group. He has been with Intel for seven years and has worked extensively in the area of process engineering on chip-attach and material-handling processes. He obtained his Bachelors degree in Mechanical Engineering from the Indian Institute of Technology, Bombay and an M.S. degree in Aeronautics from the California Institute of Technology, Pasadena, CA. His e-mail is nitin.a.deshpande at intel.com.

Mengzhi Pang
Mengzhi Pang is a Staff Packaging Engineer in the Materials Technology Development Group and has been with Intel for over three years. She has worked extensively in the areas of lead-free solder metallurgy and solder bumping technology of first-level-interconnects. Mengzhi received her Ph.D. degree in Materials Science from Washington State University and then spent three years as a postdoctoral researcher in Materials Science at Cornell University. She has more than ten U.S. patents awarded/filed and more than ten peer-reviewed journal publications. Her e-mail is mengzhi.pang at intel.com.

Ravindra Tanikella
Ravindra Tanikella received his B. Tech. degree in Chemical Engineering from Osmania University, India, and his Ph.D. degree in Chemical Engineering from the Georgia Institute of Technology. He is currently employed in the ATTD Group at Intel Corporation in Chandler, Arizona. His research interests include advanced materials and processes for microelectronics packaging. His e-mail is ravindra.v.tanikella at intel.com.

Rahul Manepalli
Rahul Manepalli is a Technology Development Manager in the ATTD Group. He currently manages the materials development efforts for large form-factor, flip-chip packages (server/graphics products), and he also manages the assembly materials path-finding team. Rahul has been with ATTD for over eight years and has worked extensively in development, integration, and certification of several generations of flip-chip and stacked die-packaging materials. Rahul obtained his B. Tech. degree in Chemical Engineering from Osmania University, Hyderabad, India and his Ph.D. degree in Chemical Engineering from the Georgia Institute of Technology, Atlanta, GA. His e-mail is rahul.n.manepalli at intel.com.

Pat Stover
Pat Stover is the Ultra-Small Form Factor Packaging Program Manager in the ATTD Group, focusing on assembly packaging, process, and material development for small, fine-pitch FC-BGA products. Pat has been with Intel, and ATTD, for twelve years where he has worked in many process engineering and technology development project management roles. Pat obtained his Bachelors degree in Chemical Engineering from the University of Illinois in 1996. His e-mail is patrick.n.stover at intel.com.

James D. Jackson
James D. Jackson has worked at Intel for 19 years in pathfinding, development and high-volume manufacturing across fab, packaging, and boards. He is currently working in ATTD as a platform-level physical interconnect architect and as the key contact for all Apple packaging issues. His Chemical Engineering degrees are from the University of Texas at Austin and the University of Washington. His e-mail is james.d.jackson at intel.com.

Ravi Mahajan
Ravi Mahajan is a Senior Principal Engineer in the ATTD Pathfinding Group responsible for packaging technology envelopes for the 22nm technology node. He also manages university research for the ATTD Group. Ravi has a Ph.D. degree from Lehigh University, an M.S. degree from the University of Houston, and a B.S. degree from the University of Bombay, all in Mechanical Engineering. He is an ASME Fellow and an IEEE Senior Member. His e-mail is ravi.v.mahajan at intel.com.

Prabhat Tiwari
Prabhat Tiwari is the 1266 Platform Manager in the ATTD Group. He has extensive experience in the area of copper interconnects and packaging technologies. He has been with Intel for eight years and has worked in PTD and FSM organizations as a backend integration manager. He obtained his Bachelors and Masters degrees from the India Institute of Technology, Kanpur, India and his Ph.D. degree in Materials Science and Engineering from N.C. State University, Raleigh, NC. His e-mail is Prabhat.tiwari at intel.com.

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