Intel's 45nm CMOS Technology

Flip-Chip Packaging Technology for Enabling 45nm Products

Neha M. Patel, Technology and Manufacturing Group, Intel Corporation
Vijay Wakharkar, Technology and Manufacturing Group, Intel Corporation
Sairam Agrahram, Technology and Manufacturing Group, Intel Corporation
Nitin Deshpande, Technology and Manufacturing Group, Intel Corporation
Mengzhi Pang, Technology and Manufacturing Group, Intel Corporation
Ravindra Tanikella, Technology and Manufacturing Group, Intel Corporation
Rahul Manepalli, Technology and Manufacturing Group, Intel Corporation
Pat Stover, Technology and Manufacturing Group, Intel Corporation
James Jackson, Technology and Manufacturing Group, Intel Corporation
Ravi Mahajan, Technology and Manufacturing Group, Intel Corporation
Prabhat Tiwari, Technology and Manufacturing Group, Intel Corporation

Index words: lead-free, flip chip, 45nm, packaging, form factor management

Citations for this paper: Agraharam, S.; Deshpande, N.; Jackson, J.; Mahajan, R.; Manepalli, R.; Pang, M.; Patel, N.; Stover, P.; Tanikella, R.; Tiwari, P.; Wakharkar, V. "Flip-Chip Packaging Technology for Enabling 45nm Products." Intel Technology Journal. http://www.intel.com/technology/itj/2008/
v12i2/7-flip/1-abstract.htm (June 2008).

ABSTRACT

Intel's packaging team has been working on developing completely Pb-free packages that can be utilized in a variety of products and market segments including the newly emerging mobile Internet devices. These technologies have been introduced into high-volume manufacturing to enable packaging of 45nm silicon devices in 2007. In order to hit this milestone, a significant number of engineering challenges had to be overcome to select and integrate the new assembly materials into the complex interconnect structure of Intel's 45nm process technology. The new solder alloys for first-level interconnect resulted in significantly higher stress on the silicon, and the Intel team reengineered many aspects of the assembly materials and process technology to resolve the crucial problem and deliver this innovative technology. The change to lead-free (Pb-free) solder alloys necessitated the development of alternate flux materials to clean off the more tenacious tin oxides from the solder surface. The new flux material had to be stable at high process temperatures as well as cleanable following the chip attach process to allow strong adhesion between the underfill, the bump metallurgy, and the die passivation. The new Pb-free, first-level interconnect architecture is superior to the older materials in many aspects, including higher current-carrying capability, and it is more reliable and environmentally friendly, being 100% Pb-free. The development of the high-k 45nm devices also enables Intel to introduce high-performance microprocessors with very low power consumption. These devices enable development of fully functional personal-computer-like features in a hand-held device. However, in order to successfully integrate a 45nm silicon chip in a hand-held device, significant reduction in the form factor of the flip-chip package was essential. In order to achieve this goal, significant technology challenges were overcome through the introduction of new underfill material and process technologies. Further reduction in the z-height required die-thinning and introduction of thinner substrates. In this paper, key technical challenges associated with Pb-free interconnect and form-factor reduction are discussed.

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