Intel's 45nm CMOS Technology

45nm Transistor Reliability

TRANSISTOR RELIABILITY FUNDAMENTALS

Transistor Bias Temperature Instability (BTI) Degradation

When subject to operating bias, transistors exhibit changes in transistor characteristics over time, an effect termed Bias Temperature Instability or BTI. Typically, transistor thresholds |(V_T)| increase, and other electrical parameters, such as drive current (I_D) and transconductance (G_m), are also affected. At typical operating fields of SiO₂ transistors, BTI is only significant for PMOS transistors with negative gate bias (NBTI).

BTI results from the creation of both interface states (D_it) and oxide trapped charges (D_ot), and the mechanism is accelerated by both voltage and temperature. As the name implies, the PMOS channel must be inverted for NBTI to occur. NBTI degradation does not require a large amount of tunneling current and can be significant even at a very low bias. Characterization of true NBTI degradation is very challenging, due to the recovery of trapping that occurs in stress upon removal of the bias. Several fast measurement techniques have been developed to minimize the recovery influence including On-The-Fly (OTF) measurements, Ultra-fast V_T measurements on the order of micro-seconds, and Pulse-IV measurements [3, 4].

Figure 4 shows a diagram of a typical PMOS NBTI degradation and recovery process well reported in the literature. There is no consensus on the exact physical mechanism, but one of the leading models for PMOS NBTI recovery is the back diffusion of Hydrogen near the substrate/dielectric interface [5].

Figure 4: PMOS NBTI vs. Time illustrating both degradation and recovery
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PMOS NBTI is recognized in the industry as a major reliability mechanism in advanced logic technologies. Degradation of maximum operating Frequency (Fmax) and circuit margin, in particular at Minimum Operating Voltage (Vmin), must be addressed within product design and testing to ensure an adequate margin to specifications over operating lifetimes.

A particularly important circuit case is SRAM memory. Transistors within the SRAM cells are typically amongst the smallest within a technology, and the SRAM Static Noise Margin (SNM) is highly sensitive to device mismatch. The scaling of SRAM memory arrays has increased the sensitivity to NBTI-induced transistor V_T mismatch, which can degrade Vmin characteristics over time. 6T SRAM cell area has traditionally reduced 2X every two years, as shown in Figure 5, which means bit counts are also increasing at a corresponding rate. In addition to design and layout approaches to improve Vmin margin, error correction techniques are often leveraged in cache designs [6].

Figure 5: 6T SRAM cell size scaling trend showing 2X cell area scaling every two years [7]
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Figure 6 shows an example of Vmin dependence on the SRAM cache array size. Both the magnitude of Vmin and the Vmin spread increase with cache array size due to transistor variations. Thus, understanding device variability at both time 0 and over time, given BTI effects, has become increasingly important with cache cell/array size scaling.

Figure 6: Vmin dependence on cache array size for 6-T SRAM [7]. Transistor aging due to PMOS NBTI will further degrade Vmin characteristics.
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PMOS NBTI remains a key concern of HK+MG CMOS transistors, and at the higher operating fields of these transistors compared to SiO₂, NMOS BTI degradation under inversion (PBTI) can also be significant [8]. Unacceptably high levels of BTI degradation for HK+MG on both NMOS and PMOS have been reported. In addition, fast charge trapping/de-trapping has also been reported on HK materials, which complicates characterization and calls the validity of conventional DC stress into question. BTI reliability degradation has been shown to be modulated by processing and integration changes such as thermal treatments, adding dopants, and nitridation techniques [9, 10]. Better charge trapping properties and improved reliability results on transistors fabricated with HK silicate dielectrics rather than HK oxides have also been reported [11].

Extensive BTI experimental data collection was undertaken in the development of Intel's 45nm HK+MG transistor technology to support reliability modeling and process optimization work. A summary of these results and a discussion of the mechanisms responsible for BTI in HK+MG transistors are presented below. We demonstrate that, with appropriate transistor architecture and processing, net BTI degradation that is comparable to, or better than, that observed with traditional SiON dielectrics, can be achieved for HK+MG dielectrics operating at ~30% higher E-fields. The optimized HK film stack used in Intel's 45nm HK+MG process also shows negligible hysteresis and transient trapping associated with fast carriers.

Gate Dielectric Breakdown, Time-Dependent Dielectric Breakdown (TDDB) and Stress-Induced Leakage Current (SILC)

The transistor gate dielectric provides isolation of the gate electrode from the conducting channel, providing the high input impedance of CMOS transistors. The reliability of the gate is, therefore, of primary importance in transistor reliability. Multiple evaluation techniques exist for assessment of gate dielectric integrity, with Time Dependent Dielectric Breakdown (TDDB) testing being the standard methodology for developing operating lifetime reliability projections. TDDB characterization is performed with elevated voltage and temperature, with either constant voltage (CVS) or constant current (CCS) on transistors or capacitors, until a failure is observed. Failure is typically based on an increase in gate current Ig, but definitions vary and can significantly impact projections.

TDDB can occur on NMOS and PMOS under all operating bias conditions (inversion, accumulation); however, the rate of dielectric damage is very strongly modulated by the band structure of the material system and, traditionally, NMOS in inversion mode tends to be the limiter for TDDB lifetime.

Although there is no rigid consensus in the literature on the exact physical mechanisms that dominate gate dielectric breakdown, it is generally attributed to a combination of several mechanisms-charge injection, interface, bulk trap state generation, and trap-assisted conduction. During operation, the electric field across the gate dielectric causes the generation of electrical defects or "traps." These traps modify the local electric field and enhance leakage current in the dielectric through various hopping and tunneling processes. With cumulative stress, more trap states are created and, consequently, a gradual increase of the gate current is observed: this is known as Stress Induced Leakage Current (SILC) degradation. Eventually, a point is reached where a conductive "chain" of traps is established between the cathode and the anode as depicted in Figure 7. The statistical theory that describes this process is called the Percolation Theory [12]. The completion of this chain results in a large increase in current flow and potentially collateral damage to the device, which may critically impact the circuit.

Figure 7: Percolation Theory describes traps as spheres of radius "r. When several of them form a complete chain from anode to cathode, breakdown (BD) occurs. The thinner the dielectric, the fewer the traps needed to cause BD [12].
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The use of HK+MG stacks to overcome scaling limitations of conventional SiO2 dielectrics introduces additional complexities in the form of materials, band structure, and interfaces that can significantly impact the TDDB mechanics and performance. Problematic HK dielectric lifetimes, SILC degradation, and interface and bulk-trap densities have been reported extensively in the literature [13, 14], and these issues need to be overcome to match the high reliability standards that have been established with conventional dielectrics.

Unless specified otherwise, TDDB stresses reported in this work were carried out with DC CVS. Monitoring of the gate leakage was performed by interrupting the stress with negligible measurement delay between stress and measurement. Care was taken to ensure that the measurement phase did not result in additional trap creation or degradation. The monitor measurements were conducted at two bias conditions corresponding to nominal and low voltage of operating conditions of products. The results focus on reliability of the optimized process flow, referred to as Final, but the affects of process optimizations are illustrated with results of material from early unoptimized process architectures and flows, referred to as Initial. Results for Intel's 65nm process are also referenced as benchmarks for mature ultra-thin SiON+PolySi devices [2].

The devices evaluated in this work are single transistors as well as arrays of transistors tied together electrically in parallel to generate large gate area structures with realistic transistor-like layouts. Each leg of the transistor arrays has a drawn gate length of 40nm while the electrical length is much smaller. The SRAM cache data reported here were collected on a fully integrated 4.5Mbit cache array. Acceleration factors were extracted through such testing to understand the sensitivity of the TDDB lifetimes to voltage and temperature. To minimize the extrapolation uncertainties in TDDB models, large sample sizes were accumulated at multiple stress condition combinations on test structures with a gate area range of over seven decades.

It will be demonstrated that, with an optimized transistor architecture and process flow, dielectric reliability comparable to that obtained on traditional SiON dielectrics can be achieved for HK+MG dielectrics operating at ~30% higher E-fields with negligible SILC prior to breakdown.

In Process Charging

It is well understood in the industry that dielectric quality as well as transistor parametric characteristics can be degraded due to process-charging induced damage from plasma processes within the fabrication flow. The charge that may accumulate on interconnect ‘antennae’ connected to transistor gates in the course of these processes can result in sufficiently high stress to induce unrecoverable changes to the transistor characteristics, or in extreme cases, even catastrophic device damage. The standard approach to protect against such plasma-induced damage is to provide a discharge path in the form of diodes or transistors. The protection needs are a function of the specific antennae connected to a device as well as the intrinsic leakage of the transistor and the charging characteristics of the fabrication processes. Design rules are defined to ensure sufficient protection to prevent any transistor damage during processing.

Process charging is one concern that has benefited from traditional dielectric scaling; increases in gate oxide leakage have made ultra thin SiO₂ dielectrics less susceptible to damage. With the large reduction in gate leakage that HK dielectrics provide, the charging rules must therefore be tightened to more historical levels.

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