Intel's 45nm CMOS Technology

45nm Design for Manufacturing

45NM MANUFACTURABILITY

Standard Cell Area Scaling

The first goal for any new process is to maintain the transistor density scaling trend. Figure 8 shows the standard cell area scaling trend. This analysis used a large standard cell library from our microprocessor designs and is weighted by typical cell usage. Transistor density scaling has followed the 0.5X density improvement per process generation. The 45nm process meets this trend despite the change to more complicated and restrictive design rules.

Figure 8: Standard cell density
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Figure 9: Within wafer variation of oscillator frequency for the 130nm through 45nm technology generations
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Variation

One of the requirements for poly patterning is scaling of variation. Figure 9 shows the within wafer variation of oscillator frequency for the 130nm through 45nm generations. The variation in frequency has remained at less than 3%. This frequency variation includes the affects of poly CD, VT, and other sources of device variation. Variation has scaled with the decreasing poly pitch, despite the changes to new transistors, changes in poly patterning, and device sizes.

Yield Learning

The final measure of success of DFM is process yield. Our yield learning trend history is shown in Figure 10. The yield learning rate on 45nm technology is as fast as previous processes and is trending toward lower defect density than the 65nm process. There is no way to measure how the DFM rules contributed to this learning. Design rules, process definition, process tools, and many other things affect the yield learning rate and final high-volume manufacturing yields. All of these things are necessary to meet the manufacturing goals.

Figure 10: Yield trend
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