Intel's 45nm CMOS Technology

  Section 7 of 12  

45nm Design for Manufacturing

OTHER LAYERS

The regular layout for poly also simplified patterning of contacts and M1. The contact pitch is the same as the gate pitch. M1 parallel to the gates has the same minimum pitch as poly.

Very restrictive rules similar to poly rules were not needed to meet process or patterning requirements for other layers, but the rules for some other layers are complex. The metal pitch choices do not need to be as restrictive as the poly layer pitches, since metal variation requirement is not as tight. The metal variation has less impact upon path delay than the poly CD variation. Metal layer design rules have some types of design rule restrictions used on poly layers on previous technologies. Printing of isolated metal lines was one of the issues on 45nm technology. Rules were added to restrict the use of isolated lines. Product layout uses several metal widths and a range of spaces. It is difficult to limit the width and pitch choices for metal, due to the need for wide lines and spaces to optimize RC delays, capacitance, and power delivery. CAD tools must change to support the changes in metal rules. One of the learnings from the 45nm technology was that the CAD tool work needs to start earlier.

  Section 7 of 12  

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