Intel's 45nm CMOS Technology

45nm Design for Manufacturing

EVOLUTION OF POLY RULES

The poly layer is one of the most difficult layers to pattern and process. Control of poly CD is one the most critical requirements in the process, due to its affect on transistor performance and variation. Poly CD control must scale for the new technology to keep the percentage variation of the channel length constant. Contacted gate pitch is a big factor in SRAM cell area and logic transistor density. These critical requirements make poly the first layer to need new pattering solutions and design rules. In the following sections, we show how poly design rules have changed over the last few processes and how DFM methodology has evolved and has been used in the definition work.

130nm Process

Our 130nm process had simple rules. There was limited early modeling of layout. Layout had random combinations of poly widths, spaces, and device orientation. Products had some issues with poly corner rounding that affected small devices. This issue was helped by DFM guidelines for layout of small devices, but the guidelines came after initial design of lead products. There was limited involvement from product design engineers in the early design-rule definition. Rule definition was primarily simple scaling of rules from previous technology generations.

90nm Process

The 90nm process included more restrictions for poly layout, and the number of poly rules increased by 47%. All devices had to be in the same orientation except for the memory bits. The difference in printing of shapes parallel and orthogonal to the scan direction was one reason for this change. Poly-over-field-routing was allowed in the X or Y orientation. The memory bit shown in Figure 4 is a unique topology with transistors in both orientations that could be modeled and characterized to account for any difference due to device orientation. Poly corner rounding and modeling were analyzed and modeled early in the definition process.

Figure 4: 90nm SRAM bit layout
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The main design impact of the one-device orientation is that a block of layout cannot be placed in two orientations, rotated 90°. I/O buffers on the top and right edges for the die must have unique layouts, even if circuits are identical. This added some layout effort, but had no affect on die size. Since there was no die size impact, the rule change was a better solution for random layout than trying to model differences due to device orientation, as was done for the memory bit.

65nm Process

The number of poly rules increased by 65% for the 65nm process, and rules were more complicated. Rules changed to allow the use of phase shift masks. All devices including the memory bit had devices in one orientation as shown in Figure 5. This layout is almost ideal for patterning with simple rectangular shapes on all layers.

Figure 5: 65nm SRAM
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There were differences in poly layout rules based upon pitch and poly space and orientation. The complex rules had little effect on transistor density. Many of the new rules affected special cases that did not occur often or were easy to fix. For example, layout of a minimum width device has some new rules for end-cap, but design did not use a lot of minimum width devices. Where they were used, the end cap rules were usually easy to meet due to area being limited by other rules.

Cell layout studies and modeling of layout increased for this generation for worst-case structures. The layout was random and it was difficult to determine all worst-case layouts.

45nm Process

Meeting the transistor density and process requirements of the 45nm technology required significant changes in design rules. The high-K metal gate transistors on this technology are the biggest change in transistors in 40 years [6]. 193nm patterning tools were needed to minimize cost and risk. Poly had to be printed using 193nm dry tools and still had to meet our need for 0.7X scaling of the pitch. Variation could not increase. The early modeling work increased significantly from the 65nm process. This included earlier involvement of the OPC experts in the design-rule definition and evaluation phases. Our goal was a more comprehensive evaluation of rules and layout topologies through modeling.

There were some changes in poly layout on the 90nm and 65nm process, but the layout has remained very random. Design could have used any poly pitch >= minimum pitch, and any channel length >=minimum was allowed. The different channel lengths could be randomly mixed. Transistors were in one orientation, but poly routing could be in either orientation. Corner rounding of poly close to devices could impact transistor performance.

Early in the definition work we asked if poly patterning in logic could be similar to the poly patterning in the SRAM bit introduced in the 65nm generation. One of the big concerns for making poly layout more regular was limiting the channel layout choices available to design. Design had always had few restrictions on the channel lengths. We wondered if this freedom was necessary. Figure 6 shows the channel lengths used in one 65nm design. Most of the devices at 0.10u and 0.11u are in the SRAM bits. The few devices at longer channel lengths were primarily in analog and I/O circuits. 99% of the devices in random logic had minimum channel length or minimum + .01u. The main reason for using longer channel length in logic was to reduce device leakage. Channel lengths can be limited in logic as long as there are options for low leakage devices. Device leakage is strongly dependent upon Le, so a very small change in Le can reduce leakage by 3X. Higher voltage can also be used to reduce leakage. There were some circuits where a longer Le device had to be replaced by two or more minimum channel length devices. Based on analysis of data like this and other layout studies, the design was partitioned into three groups: logic, analog, and SRAM. Analog and SRAM are treated as special cases.

Figure 6: Product channel lengths on 65nm design
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Figure 7: 45nm SRAM and logic poly layout
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The 45nm process has trench contacted-based local routing. This eliminated the need to use poly routing orthogonal to the transistor gate and the wide poly used for poly contacts. Layout studies were done to understand if one poly pitch was possible and how this affected rules for other layers. The local routing and limitations on transistor channel length had allowed logic poly layout to be one pitch and one direction as shown in Figure 7. The number of layout rules for logic layout was reduced by 37%. This reduction is not large, as the simple layout might indicate, because the poly rules include rules for poly spacing to other layers, and there are several rules for end-caps and poly end-to-end.

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