Intel's 45nm CMOS Technology

45nm Design for Manufacturing

DESIGN RULE DEFINITION

Modeling is the cornerstone of today's design rule definition process. Building predictive models for the new technology is one of the challenges for a new technology.

The rule definition work is front-loaded, with the rules defined before technology development is complete. Figure 1 shows the elements of the design rule definition process.

Figure 1: Design rule definition
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The transistor density scaling goal drives the 1D pitch requirement for the key layers like poly and Metal-1 (M1). This 1D pitch must scale by 0.7X per process generation. 2D rules such as line end-to-end space or minimum line length can be more difficult to scale than the 1D rules. Isolated and wide lines may have scaling problems. The techniques needed to meet the 1D scaling requirements may make scaling the 2D rules more difficult. A change in illumination technology to get good minimum line width and minimum space may not allow the same scaling of rules for wider lines, or it may make scaling of rules different for X and Y directions.

Design rules are not changed after the beginning of manufacturing ramp. Learning about difficult process issues feeds forward into the design rule definition of the new process. Some design guidelines on previous technology may become hard rules on the new technology. Some structures that caused significant process problems and/or required significant process changes may be eliminated by new rules. Device or interconnect models may be simplified by the elimination of parametric variables caused by simplified design rules.

Modeling of design rules starts with extrapolation of OPC models from the previous technology. New lithography tools, illumination techniques, enhancement techniques, and resists are evaluated to determine the best method for 1D scaling, and to understand the changes needed in other rules. Learning about the capabilities of the new tools is a continuous process during rule definition. Typical and worst-case layout topologies are analyzed to evaluate process issues like Mask Error Enhancement Factor (MEEF) and depth of focus. Test reticules are created to calibrate the models.

Cell studies are done using the rules generated from the modeling studies. Data are extracted from designs on older technologies to understand the requirements for critical layouts and how rule changes might affect design. Standard logic cells, register files, SRAM bits, and metal routing are all included in the layout studies. As rules mature, product groups are included in the evaluation. Evaluation of the patterning capabilities and the impact on layout is a continuous and iterative process until rules are final. Important layout topologies identified by design are analyzed by using the models, and they are included in new test reticules. Design rules that limit meeting the transistor density goals are evaluated with the models to understand if rules need to be changed or improved.

Figure 2 shows a typical simulation from a study of a design rule. This simulation studied the process margin for line end-to-end space as a function of line length. A high MEEF is an indication of poor process control. Some line lengths have insufficient control of the end-of-line space. This can create line-to-line shorts. One option to fix this would be to change the illumination as shown by the different lines on the graph. Another option would be to create a design rule that does not allow line lengths of 0.2 to 0.3u. If a rule change is proposed, cell layouts are done with the new rules to understand the impact on transistor design. A study may be done on data from designs on previous processes to determine if the design rule being changed is commonly used. If the rule change is shown to cause a significant change in area, we would consider other pattering solutions.

Figure 2: Length vs. MEEF
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The main process development vehicle is the X-chip test vehicle that includes large SRAM designs, process and design test structures, and process-sensitive circuits. There are earlier mask sets that include some of the rules and features of the new process, but the X-chip is the first mask set that has large circuit blocks with all of the rules. The processing of the test chip is used to validate the rules, not define the rules. There may be a few changes in rules depending on what we learn from the test chip. The number of rules that are added or changed have to be limited, because product designs will have started before the test chip is processed. As the development process continues, the justification for design rule changes becomes more difficult. By the time production starts, a design rule problem has to be fixed by process unless it is impossible to fix that way.

Figure 3 shows our trend in the number of rules over time for the 45nm process. The timeline is relative to tape-out of first design on the technology. In addition to added new rules, there were some minor changes for better and worse rule values. The number of rules increased during the design and layout of the test chip as the modeling work continued and OPC flows were developed. There was a small increase in the number of rules after processing of the test chip. These changes were not all due to patterning issues. New understanding of the transistor of metal processing can create the need for new rules. By the time masks were created for the first product, the rules were stable. There were only a few changes in design rules after the first design started. The 45nm rule stability was good, but there were more changes than desired. On the 32nm process we had fewer changes during the test chip design and after the start of the first product. Process development continued during debug of the first design, but the rules did not change during this time. Process improvement continues through the life of the process to reduce defect density, and cost, but this is done without changing design rules.

Figure 3: Changes in number of poly rules
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